A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers

Jubee Tada, Ryusuke Egawa, Kazushige Kawai, Hiroaki Kobayashi, Gensuke Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Three-dimensional (3-D) integration technologies have been expected to overcome the limitations of conventional microprocessors, which integrated by two-dimensional (2-D) implementation technologies. This paper focuses on a circuit partitioning strategy for 3-D integrated circuit designs, because it plays important roles to exploit the potential of 3-D integrated circuits. A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers is proposed and evaluated in this paper. The proposed strategy equalizes the area of each layer and avoids the critical path to across different layers as much as possible A double-precision 3-D integrated floating-point multiplier which designed by the proposed circuit partitioning strategy achieves 42% delay reduction compared to the 2-D implementation.

Original languageEnglish
Title of host publication2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
DOIs
Publication statusPublished - 2011
Event2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 - Osaka, Japan
Duration: 2012 Jan 312012 Feb 2

Publication series

Name2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

Other

Other2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
CountryJapan
CityOsaka
Period12/1/3112/2/2

Keywords

  • 3-D integration
  • TSV
  • floating-point arithmetic units

ASJC Scopus subject areas

  • Control and Systems Engineering

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