A Metadata Prefetching Mechanism for Hybrid Memory Architectures

Shunsuke Tsukada, Hikaru Takayashiki, Masayuki Sato, Kazuhiko Komatsu, Hiroaki Kobayashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A hybrid memory, which is the main memory consisting of two distinct memory devices, is expected to achieve a good balance between high performance and large capacity. However, unlike a traditional memory, the hybrid memory needs the metadata for data management and requires additional access latency for their references. To hide the latency, this paper proposes a metadata prefetching mechanism considering the address differences to control the prefetching. The evaluation results show that the proposed mechanism increases the metadata hit rate in two-thirds of the examined benchmarks and improves IPC by up to 34% and 6% on average.

Original languageEnglish
Title of host publicationIEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665415033
DOIs
Publication statusPublished - 2021 Apr 14
Event24th IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021 - Virtual, Online, Japan
Duration: 2021 Apr 142021 Apr 16

Publication series

NameIEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021 - Proceedings

Conference

Conference24th IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021
CountryJapan
CityVirtual, Online
Period21/4/1421/4/16

Keywords

  • address difference
  • hybrid memory architecture
  • metadata
  • performance
  • prefetch

ASJC Scopus subject areas

  • Hardware and Architecture

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