A Memory Using One-transistor Gain Cell on SOI(FBC) with Performance Suitable for Embedded DRAM's

Takashi Ohsawa; Tomoki Higashi; Katsuyuki Fujita; Tamio Ikehashi; Takeshi Kajiyama; Yoshiaki Fukuzumi; Tomoaki Shino; Hiroaki Yamada; Hiroomi Nakajima; Yoshihiro Minami; Takashi Yamada; Kazumi Inoh; Takeshi Hamamoto

A Memory Using One-transistor Gain Cell on SOI(FBC) with Performance Suitable for Embedded DRAM's

Takashi Ohsawa, Tomoki Higashi, Katsuyuki Fujita, Tamio Ikehashi, Takeshi Kajiyama, Yoshiaki Fukuzumi, Tomoaki Shino, Hiroaki Yamada, Hiroomi Nakajima, Yoshihiro Minami, Takashi Yamada, Kazumi Inoh, Takeshi Hamamoto

Research output: Contribution to conference › Paper › peer-review

11 Citations (Scopus)

Abstract

A 288Kbit memory chip featuring a one-transistor gain cell on SOI of the size 0.21 μ m²(7F² with F=0.175 μ m) which we named the floating body transistor cell(FBC) is presented and basic characteristics of the cell and the memory chip performance are disclosed. The threshold voltages of a cell transistor in the chip for the data "1" and for the data "0" are measured by using a direct access test circuit and a fail bit map for the 96Kbit array is obtained. A sensing scheme which was designed to eliminate the effect of cell characteristics variation due to process and temperature fluctuation as common mode noise is verified to be working and the random access time is measured to be less than 100ns. The characteristics of data hold demonstrate that the FBC can satisfy retention time specifications for some embedded memories. The access time and the data retention time show that the FBC has a potential to be used as a future embedded DRAM memory cell.

Original language	English
Pages	93-96
Number of pages	4
Publication status	Published - 2003
Externally published	Yes
Event	2003 Symposium on VLSI Circuits - Kyoto, Japan Duration: 2003 Jun 12 → 2003 Jun 14

Other

Other	2003 Symposium on VLSI Circuits
Country/Territory	Japan
City	Kyoto
Period	03/6/12 → 03/6/14

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

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title = "A Memory Using One-transistor Gain Cell on SOI(FBC) with Performance Suitable for Embedded DRAM's",

abstract = "A 288Kbit memory chip featuring a one-transistor gain cell on SOI of the size 0.21 μ m2(7F2 with F=0.175 μ m) which we named the floating body transistor cell(FBC) is presented and basic characteristics of the cell and the memory chip performance are disclosed. The threshold voltages of a cell transistor in the chip for the data {"}1{"} and for the data {"}0{"} are measured by using a direct access test circuit and a fail bit map for the 96Kbit array is obtained. A sensing scheme which was designed to eliminate the effect of cell characteristics variation due to process and temperature fluctuation as common mode noise is verified to be working and the random access time is measured to be less than 100ns. The characteristics of data hold demonstrate that the FBC can satisfy retention time specifications for some embedded memories. The access time and the data retention time show that the FBC has a potential to be used as a future embedded DRAM memory cell.",

author = "Takashi Ohsawa and Tomoki Higashi and Katsuyuki Fujita and Tamio Ikehashi and Takeshi Kajiyama and Yoshiaki Fukuzumi and Tomoaki Shino and Hiroaki Yamada and Hiroomi Nakajima and Yoshihiro Minami and Takashi Yamada and Kazumi Inoh and Takeshi Hamamoto",

year = "2003",

language = "English",

pages = "93--96",

note = "2003 Symposium on VLSI Circuits ; Conference date: 12-06-2003 Through 14-06-2003",

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T1 - A Memory Using One-transistor Gain Cell on SOI(FBC) with Performance Suitable for Embedded DRAM's

AU - Ohsawa, Takashi

AU - Higashi, Tomoki

AU - Fujita, Katsuyuki

AU - Ikehashi, Tamio

AU - Kajiyama, Takeshi

AU - Fukuzumi, Yoshiaki

AU - Shino, Tomoaki

AU - Yamada, Hiroaki

AU - Nakajima, Hiroomi

AU - Minami, Yoshihiro

AU - Yamada, Takashi

AU - Inoh, Kazumi

AU - Hamamoto, Takeshi

PY - 2003

Y1 - 2003

N2 - A 288Kbit memory chip featuring a one-transistor gain cell on SOI of the size 0.21 μ m2(7F2 with F=0.175 μ m) which we named the floating body transistor cell(FBC) is presented and basic characteristics of the cell and the memory chip performance are disclosed. The threshold voltages of a cell transistor in the chip for the data "1" and for the data "0" are measured by using a direct access test circuit and a fail bit map for the 96Kbit array is obtained. A sensing scheme which was designed to eliminate the effect of cell characteristics variation due to process and temperature fluctuation as common mode noise is verified to be working and the random access time is measured to be less than 100ns. The characteristics of data hold demonstrate that the FBC can satisfy retention time specifications for some embedded memories. The access time and the data retention time show that the FBC has a potential to be used as a future embedded DRAM memory cell.

AB - A 288Kbit memory chip featuring a one-transistor gain cell on SOI of the size 0.21 μ m2(7F2 with F=0.175 μ m) which we named the floating body transistor cell(FBC) is presented and basic characteristics of the cell and the memory chip performance are disclosed. The threshold voltages of a cell transistor in the chip for the data "1" and for the data "0" are measured by using a direct access test circuit and a fail bit map for the 96Kbit array is obtained. A sensing scheme which was designed to eliminate the effect of cell characteristics variation due to process and temperature fluctuation as common mode noise is verified to be working and the random access time is measured to be less than 100ns. The characteristics of data hold demonstrate that the FBC can satisfy retention time specifications for some embedded memories. The access time and the data retention time show that the FBC has a potential to be used as a future embedded DRAM memory cell.

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M3 - Paper

AN - SCOPUS:0141426756

SP - 93

EP - 96

T2 - 2003 Symposium on VLSI Circuits

Y2 - 12 June 2003 through 14 June 2003

ER -

A Memory Using One-transistor Gain Cell on SOI(FBC) with Performance Suitable for Embedded DRAM's

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