A memory-bandwidth-efficient word2vec accelerator using OpenCL for FPGA

Tomoki Shoji, Hasitha Muthumala Waidyasooriya, Taisuke Ono, Masanori Hariyama, Yuichiro Aoki, Yuki Kondoh, Yaoko Nakagawa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Word2vec is a word embedding method that converts words into vectors in such a way that the semantically and syntactically relevant words are closed to each other in the vector space. FPGAs can be used to design low-power accelerators for Word2vec. FPGAs use highly parallel computations which require parallel data access. Since FPGAs generally have a small external memory access bandwidth compared to CPUs and GPUs, the processing speed is often restricted. We evaluate the trade-off between bandwidth and accuracy using different fixed-point formats, and propose a memory-bandwidth-efficient FPGA accelerator by utilizing 19-bit fixed-point data. We have implemented the proposed accelerator on an Intel Arria 10 FPGA using OpenCL, and achieved upto 28% bandwidth reduction without any degradation to the computation accuracy. Since the reduced bandwidth allows us to access more data without any data access bottleneck, it is possible to increase the processing speed by increasing the degree of parallelism.

Original languageEnglish
Title of host publicationProceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages103-108
Number of pages6
ISBN (Electronic)9781728152684
DOIs
Publication statusPublished - 2019 Nov
Event7th International Symposium on Computing and Networking Workshops, CANDARW 2019 - Nagasaki, Japan
Duration: 2019 Nov 262019 Nov 29

Publication series

NameProceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019

Conference

Conference7th International Symposium on Computing and Networking Workshops, CANDARW 2019
CountryJapan
CityNagasaki
Period19/11/2619/11/29

Keywords

  • Data compression
  • FPGA
  • Machine learning
  • Natural language processing
  • Word embedding

ASJC Scopus subject areas

  • Hardware and Architecture
  • Information Systems
  • Artificial Intelligence
  • Computer Networks and Communications

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