A media-oriented vector architectural extension with a high bandwidth cache system

Ye Gao, Naoki Shoji, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Although modern SIMD extensions enable to improve the performance of MMAs, the limited parallel-processing capability and low memory bandwidth are their drawbacks to execute next generation MMAs. This paper proposes a novel media-oriented vector architectural extension (MVPX) to aim at accelerating a wide range of next generation MMAs. MVPX consists of an out-of-order vector processing mechanism (OVPM) and a high bandwidth cache system (MVP-cache). OVPM enables MVPX to take advantage of high data level parallelism for various MMAs. Meanwhile, MVP-cache can reduce the data transfer from/to off-chip memory accesses, and thus increase the sustained memory bandwidth by exploiting reusable vector data. It has a low power/area overhead approach to increasing memory bandwidth, compared with approaches to increasing the off-chip memory bandwidth. As a result, MVPX expands the potential of GPPs for next generation media processing in a power efficient way.

Original languageEnglish
Title of host publicationSymposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV
DOIs
Publication statusPublished - 2012
Event15th IEEE Symposium on Low-Powerand High-Speed Chips, COOL Chips XV - Yokohama, Japan
Duration: 2012 Apr 18 → 2012 Apr 20

Publication series

NameSymposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV

Other

Other15th IEEE Symposium on Low-Powerand High-Speed Chips, COOL Chips XV
CountryJapan
CityYokohama
Period12/4/18 → 12/4/20

Keywords

  • SIMD
  • cache
  • memory bandwidth
  • multimedia application
  • vector architecture

ASJC Scopus subject areas

  • Computer Networks and Communications

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    Gao, Y., Shoji, N., Egawa, R., Takizawa, H., & Kobayashi, H. (2012). A media-oriented vector architectural extension with a high bandwidth cache system. In Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV [6216588] (Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV). https://doi.org/10.1109/COOLChips.2012.6216588