A low-power FPGA based on self-adaptive multi-voltage control

Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a low-power FPGA that the supply voltage of each logic block autonomously changes to suit their deadlines. Dual-rail coding is used in FPGA datapaths to make data transfer time sensible in each pipeline stage. The deadline of the logic block in each pipeline stage is evaluated by comparing the data transfer time and the pipeline cycle time. When a low supply voltage does not violate the deadline, the supply voltage of the logic block is autonomously switched to the low voltage. This self-adaptive voltage control scheme saves power consumption without deteriorating the circuit performance. Moreover, level converters are unnecessary in the proposed FPGA which has a simple and efficient architecture.

Original languageEnglish
Title of host publicationISOCC 2013 - 2013 International SoC Design Conference
PublisherIEEE Computer Society
Pages166-169
Number of pages4
ISBN (Print)9781479911417
DOIs
Publication statusPublished - 2013 Jan 1
Event2013 International SoC Design Conference, ISOCC 2013 - Busan, Korea, Republic of
Duration: 2013 Nov 172013 Nov 19

Publication series

NameISOCC 2013 - 2013 International SoC Design Conference

Other

Other2013 International SoC Design Conference, ISOCC 2013
CountryKorea, Republic of
CityBusan
Period13/11/1713/11/19

Keywords

  • Asynchronous circuit
  • FPGA
  • Multiple voltage

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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