A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme

Akira Kotabe, Kenichi Osada, Naoki Kitai, Mio Fujioka, Shiro Kamohara, Masahiro Moniwa, Sadayuki Morita, Yoshikazu Saitoh

    Research output: Contribution to journalArticlepeer-review

    17 Citations (Scopus)

    Abstract

    To realize high-density SRAMs, we developed a four-transistor SRAM cell with a newly developed stacked vertical poly-silicon PMOS. The vertical poly-silicon PMOS has a gate surrounding a body that forms a channel and yields a drive current of 20 μA at 25°C. Vertical poly-silicon PMOSs are used as transfer MOSs and are stacked over the bulk NMOSs, used as driver MOSs, to reduce the size of a four-transistor SRAM cell. As a result, the size of the proposed four-transistor SRAM cell was 38% of that of a six-transistor SRAM cell. We also developed an electric-field-relaxation scheme to reduce cell leakage and a dual-word-voltage scheme to improve cell stability. By applying these two schemes to the proposed four-transistor SRAM cell, we achieved a 90% reduction in cell leakage and an improvement in cell stability.

    Original languageEnglish
    Pages (from-to)870-875
    Number of pages6
    JournalIEEE Journal of Solid-State Circuits
    Volume40
    Issue number4
    DOIs
    Publication statusPublished - 2005 Apr 1

    Keywords

    • CMOS memory circuits
    • Low standby leakage
    • SRAM
    • Vertical MOSFET

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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