A low-power field-programmable VLSI based on a fine-grained power-gating scheme

Masanori Hariyama, Shota Ishihara, Michitaka Kameyama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Abstract

This paper presents a novel asynchronous architecture of field-programmable gate arrays (FPGAs) to reduce the power consumption. To reduce the power consumption of switch blocks and clock distribution, asynchronous bit-serial architecture is proposed. To reduce the static power due to leakage current that is now comparable to the dynamic one, we propose a fine-grained power-gating scheme at each Lookup table (LUT). The proposed field-programmable VLSI is fabricated in a 90nm CMOS technology. Its power consumption is reduced to 42% compared to synchronous architecture.

Original languageEnglish
Title of host publication2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS
Pages702-705
Number of pages4
DOIs
Publication statusPublished - 2008 Oct 27
Event2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS - Knoxville, TN, United States
Duration: 2008 Aug 102008 Aug 13

Publication series

NameMidwest Symposium on Circuits and Systems
ISSN (Print)1548-3746

Other

Other2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS
CountryUnited States
CityKnoxville, TN
Period08/8/1008/8/13

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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