A low-power edge-triggered and logic-embedded flip-flop using complementary pass transistor circuit

Ki Tae Park, Tomokatsu Mizukusa, Hyo Sig Won, Hiroyuki Kurino, Mitsumasa Koyanagi

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)

Abstract

A new low power edge-triggered and logic embedded flip-flop based on complementary pass transistor circuit is proposed. This flip-flop provides small clock load, short propagation delay, single-phase clock scheme and small layout area. The flip-flop can reduce 35.2% power consumption while improving 24.7% propagation delay in comparison to conventional transmission-gate master-slave flip-flop in a standard 0.35 μm CMOS technology at 1.5 V power supply. In addition, logic functions can be embedded in the flip-flop. In 2-inputs multiplexer and flip-flop circuit, the proposed circuit can reduce 28.0% power consumption and improve 20.3% propagation delay compared to conventional circuit.

Original languageEnglish
Pages (from-to)640-644
Number of pages5
JournalIEICE Transactions on Electronics
VolumeE87-C
Issue number4
Publication statusPublished - 2004 Apr

Keywords

  • Edge-triggered
  • Flip-flop
  • Logic-embedded
  • Low-power

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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