TY - GEN
T1 - A low-power Content-Addressable Memory based on clustered-sparse networks
AU - Jarollahi, Hooman
AU - Gripon, Vincent
AU - Onizawa, Naoya
AU - Gross, Warren J.
PY - 2013
Y1 - 2013
N2 - A low-power Content-Addressable Memory (CAM) is introduced employing a new mechanism for associativity between the input tags and the corresponding address of the output data. The proposed architecture is based on a recently developed clustered-sparse network using binary-weighted connections that on-average will eliminate most of the parallel comparisons performed during a search. Therefore, the dynamic energy consumption of the proposed design is significantly lower compared to that of a conventional low-power CAM design. Given an input tag, the proposed architecture computes a few possibilities for the location of the matched tag and performs the comparisons on them to locate a single valid match. A 0.13μm CMOS technology was used for simulation purposes. The energy consumption and the search delay of the proposed design are 9.5%, and 30.4% of that of the conventional NAND architecture respectively with a 3.4% higher number of transistors.
AB - A low-power Content-Addressable Memory (CAM) is introduced employing a new mechanism for associativity between the input tags and the corresponding address of the output data. The proposed architecture is based on a recently developed clustered-sparse network using binary-weighted connections that on-average will eliminate most of the parallel comparisons performed during a search. Therefore, the dynamic energy consumption of the proposed design is significantly lower compared to that of a conventional low-power CAM design. Given an input tag, the proposed architecture computes a few possibilities for the location of the matched tag and performs the comparisons on them to locate a single valid match. A 0.13μm CMOS technology was used for simulation purposes. The energy consumption and the search delay of the proposed design are 9.5%, and 30.4% of that of the conventional NAND architecture respectively with a 3.4% higher number of transistors.
UR - http://www.scopus.com/inward/record.url?scp=84883443825&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84883443825&partnerID=8YFLogxK
U2 - 10.1109/ASAP.2013.6567594
DO - 10.1109/ASAP.2013.6567594
M3 - Conference contribution
AN - SCOPUS:84883443825
SN - 9781479904921
T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
SP - 305
EP - 308
BT - ASAP 2013 - Proceedings of the 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors
T2 - 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2013
Y2 - 5 June 2013 through 7 June 2013
ER -