A linear response single exposure CMOS image sensor with 0.5e- readout noise and 76ke- full well capacity

Shunichi Wakashima, Fumiaki Kusuhara, Rihito Kuroda, Shigetoshi Sugawa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

24 Citations (Scopus)

Abstract

A linear response single exposure CMOS image sensor approaching to the photon countable sensitivity and a high full well capacity (FWC) is developed using lateral overflow integration capacitor (LOFIC) architecture with dual gain column amplifiers, small floating diffusion (FD) capacitance (CFD) and low noise in-pixel source follower (SF) signal readout technologies. The fabricated 5.5 μm pitch 360Hx1680V pixel prototype image sensor exhibited 240 μV/e- conversion gain (CG) with 76 ke- FWC resulting in 0.5 e-rms readout noise and 104 dB dynamic range under room temperature operation.

Original languageEnglish
Title of host publication2015 Symposium on VLSI Circuits, VLSI Circuits 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
PagesC88-C89
ISBN (Electronic)9784863485020
DOIs
Publication statusPublished - 2015 Aug 31
Event29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015 - Kyoto, Japan
Duration: 2015 Jun 172015 Jun 19

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume2015-August

Other

Other29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015
Country/TerritoryJapan
CityKyoto
Period15/6/1715/6/19

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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