TY - GEN
T1 - A layer-adaptable cache hierarchy by a multiple-layer bypass mechanism
AU - Egawa, Ryusuke
AU - Saito, Ryoma
AU - Sato, Masayuki
AU - Kobayashi, Hiroaki
PY - 2019/6/6
Y1 - 2019/6/6
N2 - The cache hierarchy consists of several cache layers to hide the memory access latency in modern microprocessors, and the capacity and energy consumption of the cache hierarchy increase significantly as the number of layers and their sizes increase. However, since one cache configuration cannot fit all applications, the recent deep cache hierarchy sometimes degrades the energy efficiency of the computing system. In this paper, we propose a layer-adaptable cache hierarchy, which changes the structure of the cache hierarchy according to the memory access behavior of applications by a multiple-layer bypass mechanism. The proposal judges how each cache layer contributes to performance improvement and bypasses ineffective cache layers. Then the data arrays of the bypassed layers are disabled by controlling power supply. The evaluation results show that the proposed mechanism improves the energy efficiency of the computing system by up to 37% and 25% on average while keeping performance.
AB - The cache hierarchy consists of several cache layers to hide the memory access latency in modern microprocessors, and the capacity and energy consumption of the cache hierarchy increase significantly as the number of layers and their sizes increase. However, since one cache configuration cannot fit all applications, the recent deep cache hierarchy sometimes degrades the energy efficiency of the computing system. In this paper, we propose a layer-adaptable cache hierarchy, which changes the structure of the cache hierarchy according to the memory access behavior of applications by a multiple-layer bypass mechanism. The proposal judges how each cache layer contributes to performance improvement and bypasses ineffective cache layers. Then the data arrays of the bypassed layers are disabled by controlling power supply. The evaluation results show that the proposed mechanism improves the energy efficiency of the computing system by up to 37% and 25% on average while keeping performance.
KW - Bypassing
KW - Cache memory
KW - Energy consumption
UR - http://www.scopus.com/inward/record.url?scp=85070551386&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85070551386&partnerID=8YFLogxK
U2 - 10.1145/3337801.3337820
DO - 10.1145/3337801.3337820
M3 - Conference contribution
AN - SCOPUS:85070551386
T3 - ACM International Conference Proceeding Series
BT - Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2019
PB - Association for Computing Machinery
T2 - 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2019
Y2 - 6 June 2019 through 7 June 2019
ER -