A Josephson Adder Employing High-Gain Direct-Coupled Logic Gate

Kohji Hohkawa; Akira Ishida; Junsaku Nitta

doi:10.1109/T-ED.1984.21642

A Josephson Adder Employing High-Gain Direct-Coupled Logic Gate

Kohji Hohkawa, Akira Ishida, Junsaku Nitta

Research output: Contribution to journal › Article › peer-review

Abstract

A. wide-margin adder with a simple configuration employing high-gain direct-coupled logic gates (HDCL's) was studied. A wide-margin half-adder circuit, consisting of a single junction and three HDCL buffer gates, is proposed. In order to obtain a wide-margin circuit, gates were designed to be protective against a noise signal. The experimental circuit fabricated by a conventional Pb alloy Josephson technology with 5-μm minimum line width has shown wide-margin (more than a ± 30-percent bias signal margin) characteristics, as predicted by a computer simulation. This paper also demonstrates that the adder can be simply modified into a wide-margin full adder with a simple configuration by connecting an additional single junction and a buffer gate for a carry signal.

Original language	English
Pages (from-to)	983-987
Number of pages	5
Journal	IEEE Transactions on Electron Devices
Volume	31
Issue number	7
DOIs	https://doi.org/10.1109/T-ED.1984.21642
Publication status	Published - 1984 Jul
Externally published	Yes

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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abstract = "A. wide-margin adder with a simple configuration employing high-gain direct-coupled logic gates (HDCL's) was studied. A wide-margin half-adder circuit, consisting of a single junction and three HDCL buffer gates, is proposed. In order to obtain a wide-margin circuit, gates were designed to be protective against a noise signal. The experimental circuit fabricated by a conventional Pb alloy Josephson technology with 5-μm minimum line width has shown wide-margin (more than a ± 30-percent bias signal margin) characteristics, as predicted by a computer simulation. This paper also demonstrates that the adder can be simply modified into a wide-margin full adder with a simple configuration by connecting an additional single junction and a buffer gate for a carry signal.",

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