A high throughput/gate AES hardware architecture by compressing encryption and decryption datapaths: Toward efficient CBC-Mode implementation

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Abstract

This paper proposes a highly efficient AES hardware architecture that supports both encryption and decryption for the CBC mode. Some conventional AES architectures employ pipelining techniques to enhance the throughput and efficiency. However, such pipelined architectures are frequently unfit because many practical cryptographic applications work in the CBC mode, where block-wise parallelism is not available for encryption. In this paper, we present an efficient AES encryption/ decryption hardware design suitable for such block-chaining modes. In particular, new operation-reordering and register-retiming techniques allow us to unify the inversion circuits for encryption and decryption (i.e., SubBytes and InvSubBytes) without any delay overhead. A new unification technique for linear mappings further reduces both the area and critical delay in total. Our design employs a common loop architecture and can therefore efficiently perform even in the CBC mode. We also present a shared key scheduling datapath that can work on-the-fly in the proposed architecture. To the best of our knowledge, the proposed architecture has the shortest critical path delay and is the most efficient in terms of throughput per area among conventional AES encryption/ decryption architectures with tower-field S-boxes. We evaluate the performance of the proposed and some conventional datapaths by logic synthesis results with the TSMC 65-nm standard-cell library and Nan-Gate 45-and 15-nm open-cell libraries. As a result, we confirm that our proposed architecture achieves approximately 53–72% higher efficiency (i.e., a higher bps/GE) than any other conventional counterpart.

Original languageEnglish
Title of host publicationCryptographic Hardware and Embedded Systems - 18th International Conference, CHES 2016, Proceedings
EditorsBenedikt Gierlichs, Axel Y. Poschmann
PublisherSpringer-Verlag
Pages538-558
Number of pages21
ISBN (Print)9783662531396
DOIs
Publication statusPublished - 2016 Jan 1
Event18th International Conference on Cryptographic Hardware and Embedded Systems, CHES 2016 - Santa Barbara, United States
Duration: 2016 Aug 172016 Aug 19

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume9813 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Other

Other18th International Conference on Cryptographic Hardware and Embedded Systems, CHES 2016
CountryUnited States
CitySanta Barbara
Period16/8/1716/8/19

Keywords

  • AES
  • CBC mode
  • Hardware architectures
  • Unified encryption/ decryption architecture

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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  • Cite this

    Ueno, R., Morioka, S., Homma, N., & Aoki, T. (2016). A high throughput/gate AES hardware architecture by compressing encryption and decryption datapaths: Toward efficient CBC-Mode implementation. In B. Gierlichs, & A. Y. Poschmann (Eds.), Cryptographic Hardware and Embedded Systems - 18th International Conference, CHES 2016, Proceedings (pp. 538-558). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 9813 LNCS). Springer-Verlag. https://doi.org/10.1007/978-3-662-53140-2_26