A high-performance ASIC implementation of the 64-bit block cipher CAST-128

Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh

Research output: Contribution to journalConference article

3 Citations (Scopus)

Abstract

We propose a compact hardware architecture for the 64-bit block cipher CAST-128, which is one of the ISO/IEC 18033-3 standard algorithms. Part of the complexity of CAST-128 is its use of various S-boxes in various sequences, and three types of f-function are switched depending on the round numbers. Therefore a large amount of hardware resources are required for a straight-forward implementation. In order to create compact CAST-128 hardware, we minimized the number of S-box components, and merged the three f-functions into one arithmetic component. The CAST-128 hardware based on the proposed architecture was synthesized using 0.13-μm and 0.18-μm CMOS standard cell libraries and small, practical circuits of 26.4-39.5 Kgates and 189.9-614.7 M bps were obtained.

Original languageEnglish
Article number4253024
Pages (from-to)1859-1862
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Publication statusPublished - 2007 Sep 27
Event2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States
Duration: 2007 May 272007 May 30

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A high-performance ASIC implementation of the 64-bit block cipher CAST-128'. Together they form a unique fingerprint.

  • Cite this