A High-Density NAND EEPROM with Block-Page Programming for Microcomputer Applications

Yoshihisa Iwata, Masaki Momodomi, Tomoharu Tanaka, Hideko Oodaira, Yasuo Itoh, Ryozo Nakayama, Ryouhei Kirisawa, Seiichi Aritome, Tetsuo Endoh, Riichiro Shirota, Kazunori Ohuchi, Fuji Masuoka

Research output: Contribution to journalArticle

16 Citations (Scopus)

Abstract

A 5-V-only CMOS 4-Mb NAND EEPROM with high-speed block-page programming circuits and on-chip test circuits for evaluating the NAND-structured cell is described. This high-density EEPROM has successfully demonstrated the applicability of these techniques for micro-computer applications, which require a large nonvolatile memory system with low power consumption. 0018-9200/90/0400-0417$01.00

Original languageEnglish
Pages (from-to)417-424
Number of pages8
JournalIEEE Journal of Solid-State Circuits
Volume25
Issue number2
DOIs
Publication statusPublished - 1990 Apr
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Iwata, Y., Momodomi, M., Tanaka, T., Oodaira, H., Itoh, Y., Nakayama, R., Kirisawa, R., Aritome, S., Endoh, T., Shirota, R., Ohuchi, K., & Masuoka, F. (1990). A High-Density NAND EEPROM with Block-Page Programming for Microcomputer Applications. IEEE Journal of Solid-State Circuits, 25(2), 417-424. https://doi.org/10.1109/4.52165