Abstract
A 5-V-only CMOS 4-Mb NAND EEPROM with high-speed block-page programming circuits and on-chip test circuits for evaluating the NAND-structured cell is described. This high-density EEPROM has successfully demonstrated the applicability of these techniques for micro-computer applications, which require a large nonvolatile memory system with low power consumption. 0018-9200/90/0400-0417$01.00
Original language | English |
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Pages (from-to) | 417-424 |
Number of pages | 8 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | 25 |
Issue number | 2 |
DOIs | |
Publication status | Published - 1990 Apr |
Externally published | Yes |
ASJC Scopus subject areas
- Electrical and Electronic Engineering