A graph-based approach to designing parallel multipliers over galois fields based on normal basis representations

Kotaro Okamoto, Naofumi Homma, Takafumi Aoki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

This paper presents a graph-based approach to designing arithmetic circuits over Galois fields (GFs) using normal basis representations. The proposed method is based on a graph-based circuit description called Galois-field Arithmetic Circuit Graph (GF-ACG). First, we extend GF-ACG to describe GFs represented by normal basis in addition to polynomial basis. We then apply the extended design method to Massey-Omura parallel multipliers which are well known as typical multipliers based on normal basis. We present the formal description in a hierarchical manner and show that the verification time is greatly reduced as compared with that of the conventional simulation technique. In addition, we design GF exponentiation circuits consisting of the Massey-Omura parallel multipliers and evaluate the performance in comparison with that of polynomial-basis multipliers.

Original languageEnglish
Title of host publicationProceedings - 2013 IEEE 43rd International Symposium on Multiple-Valued Logic, ISMVL 2013
Pages158-163
Number of pages6
DOIs
Publication statusPublished - 2013
Event2013 IEEE 43rd International Symposium on Multiple-Valued Logic, ISMVL 2013 - Toyama, Japan
Duration: 2013 May 222013 May 24

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

Other

Other2013 IEEE 43rd International Symposium on Multiple-Valued Logic, ISMVL 2013
CountryJapan
CityToyama
Period13/5/2213/5/24

Keywords

  • arithmetic circuits
  • computer algebra
  • formal verification
  • normal basis

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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