A graph-based approach to designing multiple-valued arithmetic algorithms

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

This paper presents a graph-based approach to designing multiple-valued arithmetic circuits. Our method describes arithmetic circuits in a hierarchical manner with high-level multiple-valued graphs, which are determined by specific algebra and arithmetic formulae. The proposed circuit description can be effectively verified by symbolic computations such as polynomial reduction using Groebner Bases. In this paper, we describe the proposed graph representation and show an example of its description and verification. The advantageous effects of the proposed approach are demonstrated through experimental designs of parallel multipliers over Galois field GF(2m) for different word-lengths and irreducible polynomials. The result shows that the proposed approach has a definite possibility of verifying practical arithmetic circuits where the conventional simulation techniques failed.

Original languageEnglish
Title of host publicationProceedings - 41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011
Pages27-32
Number of pages6
DOIs
Publication statusPublished - 2011 Aug 18
Event41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011 - Tuusula, Finland
Duration: 2011 May 232011 May 25

Publication series

NameProceedings - 41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011

Other

Other41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011
CountryFinland
CityTuusula
Period11/5/2311/5/25

Keywords

  • arithmetic circuits
  • computer algebra
  • formal verification
  • multiple-valued logic

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Applied Mathematics

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  • Cite this

    Saito, K., Homma, N., & Aoki, T. (2011). A graph-based approach to designing multiple-valued arithmetic algorithms. In Proceedings - 41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011 (pp. 27-32). [5954204] (Proceedings - 41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011). https://doi.org/10.1109/ISMVL.2011.44