Abstract
A digit-serial, multiple valued associative memory VLSI for high-speed information search is presented. Input and output data of a processing element (PE) in the VLSI are directly encoded by appropriate multiple-valued digits, respectively, so that search operations are efficiently described by the combination of a multiple-valued down literals and pass gates. Moreover, multiple-valued memory information is stored in each PE by programming the threshold of the down literal which can be easily implemented using special MOS transistors, called floating-gate MOS transistors. It is demonstrated that the number of interconnections and transistors in the 5-valued associative memory can be reduced to 25% and 53%, respectively, in comparison with the corresponding binary implementation.
Original language | English |
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Title of host publication | Proceedings of The International Symposium on Multiple-Valued Logic |
Publisher | Publ by IEEE |
Pages | 24-31 |
Number of pages | 8 |
ISBN (Print) | 0818621451 |
Publication status | Published - 1991 May 1 |
Event | Proceedings of the 21st International Symposium on Multiple-Valued Logic - Victoria, BC, Can Duration: 1991 May 26 → 1991 May 29 |
Other
Other | Proceedings of the 21st International Symposium on Multiple-Valued Logic |
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City | Victoria, BC, Can |
Period | 91/5/26 → 91/5/29 |
ASJC Scopus subject areas
- Chemical Health and Safety
- Hardware and Architecture
- Safety, Risk, Reliability and Quality
- Logic