A floating-gate-MOS-based multiple-valued associative memory

Takahiro Hanyu, Tatsuo Higuchi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A digit-serial, multiple valued associative memory VLSI for high-speed information search is presented. Input and output data of a processing element (PE) in the VLSI are directly encoded by appropriate multiple-valued digits, respectively, so that search operations are efficiently described by the combination of a multiple-valued down literals and pass gates. Moreover, multiple-valued memory information is stored in each PE by programming the threshold of the down literal which can be easily implemented using special MOS transistors, called floating-gate MOS transistors. It is demonstrated that the number of interconnections and transistors in the 5-valued associative memory can be reduced to 25% and 53%, respectively, in comparison with the corresponding binary implementation.

Original languageEnglish
Title of host publicationProceedings of The International Symposium on Multiple-Valued Logic
PublisherPubl by IEEE
Pages24-31
Number of pages8
ISBN (Print)0818621451
Publication statusPublished - 1991 May 1
EventProceedings of the 21st International Symposium on Multiple-Valued Logic - Victoria, BC, Can
Duration: 1991 May 261991 May 29

Other

OtherProceedings of the 21st International Symposium on Multiple-Valued Logic
CityVictoria, BC, Can
Period91/5/2691/5/29

ASJC Scopus subject areas

  • Chemical Health and Safety
  • Hardware and Architecture
  • Safety, Risk, Reliability and Quality
  • Logic

Fingerprint Dive into the research topics of 'A floating-gate-MOS-based multiple-valued associative memory'. Together they form a unique fingerprint.

  • Cite this

    Hanyu, T., & Higuchi, T. (1991). A floating-gate-MOS-based multiple-valued associative memory. In Proceedings of The International Symposium on Multiple-Valued Logic (pp. 24-31). Publ by IEEE.