A floating-gate-MOS-based multiple-valued associative memory

Takahiro Hanyu; Tatsuo Higuchi

A floating-gate-MOS-based multiple-valued associative memory

Takahiro Hanyu, Tatsuo Higuchi

Systems & Software Division

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

A digit-serial, multiple valued associative memory VLSI for high-speed information search is presented. Input and output data of a processing element (PE) in the VLSI are directly encoded by appropriate multiple-valued digits, respectively, so that search operations are efficiently described by the combination of a multiple-valued down literals and pass gates. Moreover, multiple-valued memory information is stored in each PE by programming the threshold of the down literal which can be easily implemented using special MOS transistors, called floating-gate MOS transistors. It is demonstrated that the number of interconnections and transistors in the 5-valued associative memory can be reduced to 25% and 53%, respectively, in comparison with the corresponding binary implementation.

Original language	English
Title of host publication	Proceedings of The International Symposium on Multiple-Valued Logic
Publisher	Publ by IEEE
Pages	24-31
Number of pages	8
ISBN (Print)	0818621451
Publication status	Published - 1991 May 1
Event	Proceedings of the 21st International Symposium on Multiple-Valued Logic - Victoria, BC, Can Duration: 1991 May 26 → 1991 May 29

Other

Other	Proceedings of the 21st International Symposium on Multiple-Valued Logic
City	Victoria, BC, Can
Period	91/5/26 → 91/5/29

ASJC Scopus subject areas

Chemical Health and Safety
Hardware and Architecture
Safety, Risk, Reliability and Quality
Logic

Cite this

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title = "A floating-gate-MOS-based multiple-valued associative memory",

abstract = "A digit-serial, multiple valued associative memory VLSI for high-speed information search is presented. Input and output data of a processing element (PE) in the VLSI are directly encoded by appropriate multiple-valued digits, respectively, so that search operations are efficiently described by the combination of a multiple-valued down literals and pass gates. Moreover, multiple-valued memory information is stored in each PE by programming the threshold of the down literal which can be easily implemented using special MOS transistors, called floating-gate MOS transistors. It is demonstrated that the number of interconnections and transistors in the 5-valued associative memory can be reduced to 25% and 53%, respectively, in comparison with the corresponding binary implementation.",

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N2 - A digit-serial, multiple valued associative memory VLSI for high-speed information search is presented. Input and output data of a processing element (PE) in the VLSI are directly encoded by appropriate multiple-valued digits, respectively, so that search operations are efficiently described by the combination of a multiple-valued down literals and pass gates. Moreover, multiple-valued memory information is stored in each PE by programming the threshold of the down literal which can be easily implemented using special MOS transistors, called floating-gate MOS transistors. It is demonstrated that the number of interconnections and transistors in the 5-valued associative memory can be reduced to 25% and 53%, respectively, in comparison with the corresponding binary implementation.

AB - A digit-serial, multiple valued associative memory VLSI for high-speed information search is presented. Input and output data of a processing element (PE) in the VLSI are directly encoded by appropriate multiple-valued digits, respectively, so that search operations are efficiently described by the combination of a multiple-valued down literals and pass gates. Moreover, multiple-valued memory information is stored in each PE by programming the threshold of the down literal which can be easily implemented using special MOS transistors, called floating-gate MOS transistors. It is demonstrated that the number of interconnections and transistors in the 5-valued associative memory can be reduced to 25% and 53%, respectively, in comparison with the corresponding binary implementation.

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M3 - Conference contribution

AN - SCOPUS:0026155388

SN - 0818621451

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EP - 31

BT - Proceedings of The International Symposium on Multiple-Valued Logic

PB - Publ by IEEE

T2 - Proceedings of the 21st International Symposium on Multiple-Valued Logic

Y2 - 26 May 1991 through 29 May 1991

ER -

A floating-gate-MOS-based multiple-valued associative memory

Abstract

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ASJC Scopus subject areas

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