A fine-grained programmable logic module with small amount of configuration data for dynamically reconfigurable field-programmable gate array

Dynamically customizable and reconfigurable hardware architecture for a specific task on demand is one of the most important issues to bring out a novel-computing paradigm in the era of system LSIs. Our target is to realize a flexible processor which is a kind of dynamically reconfigurable field-programmable gate array (FPGA) and is able to execute signal processing while reading the next configuration data (CD) simultaneously. In order to realize the flexible processor, since the amount of CD is enormous in conventional FPGAs, it is necessary to reduce the amount of CD as much as possible. In this paper, we propose a newly developed programmable logic module that can reduce the amount of CD to no less than 86% of that for the conventional Look Up Table (LUT)-based programmable logic module.