A field-programmable VLSI processor based on direct allocation of a control/data flow graph

Naotaka Ohsawa, Masanori Hariyama, Michitaka Kameyama

Research output: Contribution to journalArticlepeer-review

Abstract

The next generation of information systems will require the development of special-purpose processors that can accommodate computation-intensive algorithms at superhigh speeds. Design methods based on field-programmable gate arrays (FPGA), which can guide the fabrication of special-use processors at lower cost than ad hoc design methods, are attracting increased attention. However, special-purpose processors based on FPGA have the problem of poor performance compared to processors designed by ad hoc methods. In this article, we propose to eliminate this problem with FPGA processors by using field-programmable VLSI (or FPVLSI) arrays of processing elements in which data transfer takes place between nearest-neighbor processors only, direct allocation of control/data flow graphs, and bit-serial architecture. Furthermore, we show that when this FPVLSI approach is used to implement a 16-point FFT, the resulting processor module is over 20 times faster than a currently available FPGA module with the same area.

Original languageEnglish
Pages (from-to)28-37
Number of pages10
JournalElectronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)
Volume87
Issue number7
DOIs
Publication statusPublished - 2004 Jul 1

Keywords

  • Bit-serial architecture
  • FPGA
  • Processor allocation
  • Special-purpose processor

ASJC Scopus subject areas

  • Physics and Astronomy(all)
  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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