A field-programmable digital filter chip using multiple-valued current-mode logic

Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi

Research output: Contribution to journalConference articlepeer-review

4 Citations (Scopus)

Abstract

This paper presents a Field-Programmable Digital Filter (FPDF) IC that employs carry-propagation-free redundant arithmetic algorithms for faster computation and multiple-valued current-mode circuit technology for high-density low-power implementation. The prototype FPDF fabrication with 0.6μm CMOS technology demonstrates that the chip area and power consumption can be reduced to 41% and 74%, respectively, compared with the standard binary logic implementation.

Original languageEnglish
Pages (from-to)213-220
Number of pages8
JournalProceedings of The International Symposium on Multiple-Valued Logic
Publication statusPublished - 2003 Jul 21
EventThirty-third International Symposium on Multiple-Valued Logic - Tokyo, Japan
Duration: 2003 May 162003 May 19

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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