This paper presents a Field-Programmable Digital Filter (FPDF) IC that employs carry-propagation-free redundant arithmetic algorithms for faster computation and multiple-valued current-mode circuit technology for high-density low-power implementation. The prototype FPDF fabrication with 0.6μm CMOS technology demonstrates that the chip area and power consumption can be reduced to 41% and 74%, respectively, compared with the standard binary logic implementation.
|Number of pages||8|
|Journal||Proceedings of The International Symposium on Multiple-Valued Logic|
|Publication status||Published - 2003 Jul 21|
|Event||Thirty-third International Symposium on Multiple-Valued Logic - Tokyo, Japan|
Duration: 2003 May 16 → 2003 May 19
ASJC Scopus subject areas
- Computer Science(all)