A fast hardware/software co-verification method for System-On-a-Chip by using a C/C++ simulator and FPGA emulator with shared register communication

Yuichi Nakamura, Kouhei Hosokawa, Ichiro Kuroda, Ko Yoshikawa, Takeshi Yoshimura

Research output: Contribution to journalConference articlepeer-review

52 Citations (Scopus)

Abstract

This paper describes a new hardware/software co-verification method for System-On-a-Chip, based on the integration of a C/C++ simulator and an inexpensive FPGA emulator. Communication between the simulator and emulator occurs via a flexible interface based on shared communication registers. This method enables easy debugging, rich portability, and high verification speed, at a low cost. We describe the application of this environment to the verification of three different complex commercial SoCs, supporting concurrent hardware and embedded software development. In these projects, our verification methodology was used to perform complete system verification at 0.2-1.1 MHz, while supporting full graphical interface functions such as "waveform" or "signal dump" viewers, and debugging functions such as "step" or "break".

Original languageEnglish
Pages (from-to)299-304
Number of pages6
JournalProceedings - Design Automation Conference
DOIs
Publication statusPublished - 2004
Externally publishedYes
EventProceedings of the 41st Design Automation Conference - San Diego, CA, United States
Duration: 2004 Jun 72004 Jun 11

Keywords

  • Co-Verification
  • FPGA Emulation

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

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