A Fail‐safe Logic Operator Using an Insulated Planar Transformer

Norihiro Asada, Hidetoshi Matsuki, Masayoshi Esashi

Research output: Contribution to journalArticlepeer-review

Abstract

A fail‐safe logic circuit must switch the output signal to the logical value “0” when an operation circuit fails. A transformer has such favorable characteristics for fail‐safe logic circuits as only the magnetic flux change is transmitted and a superposition of magnetic flux is realized. Thus those characteristics arc applied to a failsafe logic operator. A new fail‐safe logic operator using an insulated planar transformer was developed for a fail‐safe majority operation and a fail‐safe interlocking. In this paper, the principle, structure, design and fundamental characteristics of the new fail‐safe logic operator are described.

Original languageEnglish
Pages (from-to)115-122
Number of pages8
JournalElectrical Engineering in Japan
Volume115
Issue number2
DOIs
Publication statusPublished - 1995

Keywords

  • Fail‐safe
  • failure analysis
  • interlock
  • majority logic operation
  • planar transformer.

ASJC Scopus subject areas

  • Energy Engineering and Power Technology
  • Electrical and Electronic Engineering

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