A dynamically reconfigurable SIMD processor for a vision chip

Takashi Komuro, Shingo Kagami, Masatoshi Ishikawa

Research output: Contribution to journalArticlepeer-review

108 Citations (Scopus)

Abstract

Conventional SIMD image processors are very effective for early visual processing because of their parallelism. However, in performing more advanced processing, they exhibit some problems, such as poor performance in global operations and a tradeoff between flexibility of processing and the number of pixels. This paper shows a new architecture and sample algorithms of a vision chip that has the ability to reconfigure its hardware dynamically by chaining processing elements. A prototype chip with 64 × 64 pixels manufactured using the 0.35-μm CMOS process is also shown.

Original languageEnglish
Pages (from-to)265-268
Number of pages4
JournalIEEE Journal of Solid-State Circuits
Volume39
Issue number1
DOIs
Publication statusPublished - 2004 Jan 1
Externally publishedYes

Keywords

  • High-speed image processing
  • Massively parallel processing
  • Reconfigurable
  • Single instruction multiple data (SIMD)
  • Vision chip

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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