A dynamically reconfigurable IP for data-intensive applications

Naoto Miyamoto, Leo Karnan, Koji Kotani, Tadahiro Ohmi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we introduce a report on designing an ASIC which includes a dynamically reconfigurable IP that can change composition within a clock cycle. Empirical design TAT evaluations were made and the results showed that a data-intensive processor equipped with this IP can be designed in 4 weeks.

Original languageEnglish
Title of host publicationProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
Pages404-405
Number of pages2
Publication statusPublished - 2004 Dec 1
EventProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits - Fukuoka, Japan
Duration: 2004 Aug 42004 Aug 5

Publication series

NameProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits

Other

OtherProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
CountryJapan
CityFukuoka
Period04/8/404/8/5

ASJC Scopus subject areas

  • Engineering(all)

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