TY - GEN
T1 - A dynamically reconfigurable IP for data-intensive applications
AU - Miyamoto, Naoto
AU - Karnan, Leo
AU - Kotani, Koji
AU - Ohmi, Tadahiro
PY - 2004/12/1
Y1 - 2004/12/1
N2 - In this paper, we introduce a report on designing an ASIC which includes a dynamically reconfigurable IP that can change composition within a clock cycle. Empirical design TAT evaluations were made and the results showed that a data-intensive processor equipped with this IP can be designed in 4 weeks.
AB - In this paper, we introduce a report on designing an ASIC which includes a dynamically reconfigurable IP that can change composition within a clock cycle. Empirical design TAT evaluations were made and the results showed that a data-intensive processor equipped with this IP can be designed in 4 weeks.
UR - http://www.scopus.com/inward/record.url?scp=14544292051&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=14544292051&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:14544292051
SN - 078038637X
T3 - Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
SP - 404
EP - 405
BT - Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
T2 - Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
Y2 - 4 August 2004 through 5 August 2004
ER -