A dynamically-reconfigurable image recognition processor

Kazuyuki Maruo, Masayoshi Ichikawa, Naoto Miyamoto, Leo Karnan, Takahiro Yamaguchi, Koji Kotani, Tadahiro Ohmi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper introduces a new image recognition processor using a run-time reconfiguration (RTR) technology. A phase impulse response function (PIRF) is employed as an application for evaluating the performance of RTR architecture. By utilizing the RTR architecture effectively, a complicated image processing application such as PIRF can be implemented on a single processor. To achieve this, a dynamically-reconfigurable arithmetic logic unit (DRALU) is proposed. Simulation results show that our proposed processor using DRALU can execute the PIRF within 30 msec.

Original languageEnglish
Title of host publicationProceedings - 18th International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM)
Pages2075-2080
Number of pages6
Publication statusPublished - 2004
EventProceedings - 18th International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM) - Santa Fe, NM, United States
Duration: 2004 Apr 262004 Apr 30

Publication series

NameProceedings - International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM)
Volume18

Other

OtherProceedings - 18th International Parallel and Distributed Processing Symposium, IPDPS 2004 (Abstracts and CD-ROM)
Country/TerritoryUnited States
CitySanta Fe, NM
Period04/4/2604/4/30

ASJC Scopus subject areas

  • Engineering(all)

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