TY - GEN
T1 - A dynamically reconfigurable architecture combining pixel-level SIMD and operation-pipeline modes for high frame rate visual processing
AU - Iwata, Nao
AU - Kagami, Shingo
AU - Hashimoto, Koichi
PY - 2007/12/1
Y1 - 2007/12/1
N2 - This paper describes a new reconfigurable processor architecture specialized for high frame rate visual processing. This architecture employs a 2-D mesh processing element (PE) array in which the PEs can be configured to operate as SIMD arrays or operation-pipeline trees depending on image processing algorithms so that maximum on-chip memory consumption is reduced. To achieve high on-chip memory utilization, the architecture features that the instruction register in each PE is mapped in its local memory space and that the ALU network and the local memory network can be configured independently. Simulation results show that the proposed architecture effectively utilizes both of the SIMD and operation pipeline modes.
AB - This paper describes a new reconfigurable processor architecture specialized for high frame rate visual processing. This architecture employs a 2-D mesh processing element (PE) array in which the PEs can be configured to operate as SIMD arrays or operation-pipeline trees depending on image processing algorithms so that maximum on-chip memory consumption is reduced. To achieve high on-chip memory utilization, the architecture features that the instruction register in each PE is mapped in its local memory space and that the ALU network and the local memory network can be configured independently. Simulation results show that the proposed architecture effectively utilizes both of the SIMD and operation pipeline modes.
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U2 - 10.1109/FPT.2007.4439276
DO - 10.1109/FPT.2007.4439276
M3 - Conference contribution
AN - SCOPUS:50149103942
SN - 1424414725
SN - 9781424414727
T3 - ICFPT 2007 - International Conference on Field Programmable Technology
SP - 321
EP - 324
BT - ICFPT 2007 - International Conference on Field Programmable Technology
T2 - International Conference on Field Programmable Technology, ICFPT 2007
Y2 - 12 December 2007 through 14 December 2007
ER -