A dynamically reconfigurable architecture combining pixel-level SIMD and operation-pipeline modes for high frame rate visual processing

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

This paper describes a new reconfigurable processor architecture specialized for high frame rate visual processing. This architecture employs a 2-D mesh processing element (PE) array in which the PEs can be configured to operate as SIMD arrays or operation-pipeline trees depending on image processing algorithms so that maximum on-chip memory consumption is reduced. To achieve high on-chip memory utilization, the architecture features that the instruction register in each PE is mapped in its local memory space and that the ALU network and the local memory network can be configured independently. Simulation results show that the proposed architecture effectively utilizes both of the SIMD and operation pipeline modes.

Original languageEnglish
Title of host publicationICFPT 2007 - International Conference on Field Programmable Technology
Pages321-324
Number of pages4
DOIs
Publication statusPublished - 2007 Dec 1
EventInternational Conference on Field Programmable Technology, ICFPT 2007 - Kitakyushu, Japan
Duration: 2007 Dec 122007 Dec 14

Publication series

NameICFPT 2007 - International Conference on Field Programmable Technology

Other

OtherInternational Conference on Field Programmable Technology, ICFPT 2007
CountryJapan
CityKitakyushu
Period07/12/1207/12/14

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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