This paper describes novel high-speed selector circuits based on the distributed circuit approach and their circuit design methodologies. Two types of distributed selectors are designed and fabricated using 0.16-• m GaAs MESFET's with multilayer-interconnection structure. Both basically consist of eight stages of series-gated source-coupled field-effect transistor (FET) logic (SCFL) selector cell units laid out in a distributed fashion. The second circuit incorporates additional functions: a data input level shifter in each cell to make an SCFL interface for the data input and a balun for single-balance transformation of the clock input. A small-signal distributed amplifier design is extended to a large-signal distributed logic IC design, taking dynamic variations in transistor parameters into consideration. The error-free operation of both fabricated distributed selector IC's is confirmed at up to 40 Gbit/s, and the first IC still exhibited eye opening with 130-mV voltage swing of the inside measurement at 70 Gbit/s, which reaches 80% of f T of the fabricated FET. These distributed selector IC's successfully exhibit eye opening at higher bit rates compared to the conventional lumped-element design selector.
- Distributed circuit design
- GaAs MESFET
- Multilayer-interconnection structure
- Selector circuit
ASJC Scopus subject areas
- Electrical and Electronic Engineering