A Digit-serial reconfigurable VLSI based on quaternary inter-cell data transfer scheme

Xu Bai, Nobuaki Okada, Michitaka Kameyama

Research output: Contribution to journalArticlepeer-review

Abstract

A high-throughput reconfigurable VLSI using a digit-serial architecture is proposed, where two-bit data for each operand enters a cell per clock cycle. The interconnection complexity between two adjacent cells is reduced by using a quaternary inter-cell data transfer scheme. In a cell, the quaternary data is converted into binary dual-rail voltage signals, and binary-controlled current steering technique is introduced utilizing a programmable three-level differential-pair circuit to implement an arbitrary two-variable binary logic function and a full-adder sum/carry. In the cell output circuit, switched current sources are used to reduce power dissipation. Moreover, the CMOS logic is used to make driving capability of a D flip-flop high. As a result, the maximum throughput of the proposed digit-serial reconfigurable VLSI using quaternary cells is twice that of the bit-serial reconfigurableVLSI, while the power-delay product is reduced to 74%. Dramatic improvement of the reconfigurable VLSI can be achieved.

Original languageEnglish
Pages (from-to)1-18
Number of pages18
JournalJournal of Multiple-Valued Logic and Soft Computing
Volume20
Issue number1-2
Publication statusPublished - 2012 Dec 28

Keywords

  • Digit-serial architecture
  • Fine-grain reconfigurable VLSI
  • High throughput
  • Low power consumption.
  • MOS current-mode logic
  • Multiple-valued VLSI
  • Multiple-valued source-coupled logic

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Logic

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