A design guideline of parasitic inductance for preventing oscillatory false triggering of fast switching GaN-FET

Kazuhiro Umetani, Keisuke Yagyu, Eiji Hiraki

Research output: Contribution to journalArticlepeer-review

12 Citations (Scopus)

Abstract

Gallium nitride field-effect transistors (GaN-FETs) are attractive devices because of its low on-state resistance and fast switching capability. However, they can suffer from false triggering caused by fast switching. Particularly, a disastrous oscillation of repetitive false triggering can occur after a turn-off, which may deteriorate the reliability of power converters. To address this issue, we give a design guideline to prevent this phenomenon. We analyze a simple circuit model to derive the condition of occurrence of this phenomenon, which is then verified experimentally. Results show that the parasitic inductance of the gating circuit, Lg, and that of the decoupling circuit, Ld, should be designed so that the LC resonance frequency of Lg and the gate–source capacitance of the GaN-FET does not coincide with that of Ld and the drain–source capacitance, respectively.

Original languageEnglish
Pages (from-to)S84-S90
JournalIEEJ Transactions on Electrical and Electronic Engineering
Volume11
DOIs
Publication statusPublished - 2016 Dec 1
Externally publishedYes

Keywords

  • GaN-FET
  • false triggering
  • parasitic inductance
  • self turn-on
  • self-oscillation
  • switching noise

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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