A Design Framework for Invertible Logic

Naoya Onizawa; Kaito Nishino; Sean C. Smithson; Brett H. Meyer; Warren J. Gross; Hitoshi Yamagata; Hiroyuki Fujita; Takahiro Hanyu

doi:10.1109/TCAD.2020.3003906

A Design Framework for Invertible Logic

Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu

Systems & Software Division

Research output: Contribution to journal › Article › peer-review

4 Citations (Scopus)

Abstract

Invertible logic using a probabilistic magnetoresistive device model has been recently presented that can compute functions in bidirectional ways and solve several problems quickly, such as factorization and combinational optimization. In this article, we present a design framework for invertible logic circuits. Our approach makes use of linear programming to create a Hamiltonian library with the minimum number of nodes for small invertible-logic functions. In addition, as the device model is approximated based on stochastic computing in synthesizable SystemVerilog, a faster simulation using the compiled SystemC binary is realized than a conventional SPICE-level simulation and is verified using field-programmable gate array (FPGA) as prototyping. Using our design framework, several invertible-logic circuits are designed and emulated (verified) in SystemC, exhibiting five order-of-magnitude faster simulation than conventional work.

Original language	English
Article number	9122022
Pages (from-to)	655-665
Number of pages	11
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	40
Issue number	4
DOIs	https://doi.org/10.1109/TCAD.2020.3003906
Publication status	Published - 2021 Apr

Keywords

Field-programmable gate array (FPGA)
Hamiltonian
SystemVerilog model
stochastic computing

ASJC Scopus subject areas

Software
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

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10.1109/TCAD.2020.3003906

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title = "A Design Framework for Invertible Logic",

abstract = "Invertible logic using a probabilistic magnetoresistive device model has been recently presented that can compute functions in bidirectional ways and solve several problems quickly, such as factorization and combinational optimization. In this article, we present a design framework for invertible logic circuits. Our approach makes use of linear programming to create a Hamiltonian library with the minimum number of nodes for small invertible-logic functions. In addition, as the device model is approximated based on stochastic computing in synthesizable SystemVerilog, a faster simulation using the compiled SystemC binary is realized than a conventional SPICE-level simulation and is verified using field-programmable gate array (FPGA) as prototyping. Using our design framework, several invertible-logic circuits are designed and emulated (verified) in SystemC, exhibiting five order-of-magnitude faster simulation than conventional work.",

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author = "Naoya Onizawa and Kaito Nishino and Smithson, {Sean C.} and Meyer, {Brett H.} and Gross, {Warren J.} and Hitoshi Yamagata and Hiroyuki Fujita and Takahiro Hanyu",

note = "Funding Information: Manuscript received October 8, 2019; revised January 30, 2020; accepted June 4, 2020. Date of publication June 22, 2020; date of current version March 19, 2021. This work was supported in part by Brainware LSI Project of MEXT, Japan, JST PRESTO under Grant JPMJPR18M5, and in part by Canon Medical Systems Corporation. This article was recommended by Associate Editor J. Cortadella. (Corresponding author: Naoya Onizawa.) Naoya Onizawa, Kaito Nishino, and Takahiro Hanyu are with the Research Institute of Electrical Communication, Tohoku University, Sendai 980-8577, Japan (e-mail: naoya.onizawa.a7@tohoku.ac.jp; hanyu@riec.tohoku.ac.jp). Publisher Copyright: {\textcopyright} 1982-2012 IEEE.",

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AU - Onizawa, Naoya

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AU - Fujita, Hiroyuki

AU - Hanyu, Takahiro

N1 - Funding Information: Manuscript received October 8, 2019; revised January 30, 2020; accepted June 4, 2020. Date of publication June 22, 2020; date of current version March 19, 2021. This work was supported in part by Brainware LSI Project of MEXT, Japan, JST PRESTO under Grant JPMJPR18M5, and in part by Canon Medical Systems Corporation. This article was recommended by Associate Editor J. Cortadella. (Corresponding author: Naoya Onizawa.) Naoya Onizawa, Kaito Nishino, and Takahiro Hanyu are with the Research Institute of Electrical Communication, Tohoku University, Sendai 980-8577, Japan (e-mail: naoya.onizawa.a7@tohoku.ac.jp; hanyu@riec.tohoku.ac.jp). Publisher Copyright: © 1982-2012 IEEE.

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A Design Framework for Invertible Logic

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Keywords

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