A Design Framework for Invertible Logic

N. Onizawa, K. Nishino, S. Smithson, B. Meyer, W. Gross, H. Yamagata, H. Fujita, Takahiro Hanyu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Invertible logic using a probabilistic magnetoresistive device model has been recently presented that can operate in bidirectional ways and solve several problems quickly, such as factorization and combinational optimization. In this paper, we present a design framework for large-scale invertible logic circuits. Our approach makes use of linear programming to create a Hamiltonian library with the minimum number of nodes. In addition, as the device model is approximated based on stochastic computing in SystemVerilog, a faster simulation using the compiled SystemC binary is realized than a conventional SPICE-level simulation. We have evaluated our framework on designing invertible multipliers, which realizes almost 5 order-of-magnitude faster simulation than a conventional method.

Original languageEnglish
Title of host publicationConference Record - 53rd Asilomar Conference on Circuits, Systems and Computers, ACSSC 2019
EditorsMichael B. Matthews
PublisherIEEE Computer Society
Pages312-316
Number of pages5
ISBN (Electronic)9781728143002
DOIs
Publication statusPublished - 2019 Nov
Event53rd Asilomar Conference on Circuits, Systems and Computers, ACSSC 2019 - Pacific Grove, United States
Duration: 2019 Nov 32019 Nov 6

Publication series

NameConference Record - Asilomar Conference on Signals, Systems and Computers
Volume2019-November
ISSN (Print)1058-6393

Conference

Conference53rd Asilomar Conference on Circuits, Systems and Computers, ACSSC 2019
CountryUnited States
CityPacific Grove
Period19/11/319/11/6

Keywords

  • FPGA
  • Hamiltonian
  • Stochastic computing
  • SystemVer-ilog model

ASJC Scopus subject areas

  • Signal Processing
  • Computer Networks and Communications

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