TY - GEN
T1 - A Design Framework for Invertible Logic
AU - Onizawa, N.
AU - Nishino, K.
AU - Smithson, S.
AU - Meyer, B.
AU - Gross, W.
AU - Yamagata, H.
AU - Fujita, H.
AU - Hanyu, T.
N1 - Funding Information:
ACKNOWLEDGMENT This work was supported by Brainware LSI project of MEXT, Japan, JST PRESTO Grant Number JPMJPR18M5,
Publisher Copyright:
© 2019 IEEE.
PY - 2019/11
Y1 - 2019/11
N2 - Invertible logic using a probabilistic magnetoresistive device model has been recently presented that can operate in bidirectional ways and solve several problems quickly, such as factorization and combinational optimization. In this paper, we present a design framework for large-scale invertible logic circuits. Our approach makes use of linear programming to create a Hamiltonian library with the minimum number of nodes. In addition, as the device model is approximated based on stochastic computing in SystemVerilog, a faster simulation using the compiled SystemC binary is realized than a conventional SPICE-level simulation. We have evaluated our framework on designing invertible multipliers, which realizes almost 5 order-of-magnitude faster simulation than a conventional method.
AB - Invertible logic using a probabilistic magnetoresistive device model has been recently presented that can operate in bidirectional ways and solve several problems quickly, such as factorization and combinational optimization. In this paper, we present a design framework for large-scale invertible logic circuits. Our approach makes use of linear programming to create a Hamiltonian library with the minimum number of nodes. In addition, as the device model is approximated based on stochastic computing in SystemVerilog, a faster simulation using the compiled SystemC binary is realized than a conventional SPICE-level simulation. We have evaluated our framework on designing invertible multipliers, which realizes almost 5 order-of-magnitude faster simulation than a conventional method.
KW - FPGA
KW - Hamiltonian
KW - Stochastic computing
KW - SystemVer-ilog model
UR - http://www.scopus.com/inward/record.url?scp=85083328773&partnerID=8YFLogxK
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U2 - 10.1109/IEEECONF44664.2019.9048700
DO - 10.1109/IEEECONF44664.2019.9048700
M3 - Conference contribution
AN - SCOPUS:85083328773
T3 - Conference Record - Asilomar Conference on Signals, Systems and Computers
SP - 312
EP - 316
BT - Conference Record - 53rd Asilomar Conference on Circuits, Systems and Computers, ACSSC 2019
A2 - Matthews, Michael B.
PB - IEEE Computer Society
T2 - 53rd Asilomar Conference on Circuits, Systems and Computers, ACSSC 2019
Y2 - 3 November 2019 through 6 November 2019
ER -