A Design Framework for Invertible Logic

N. Onizawa; K. Nishino; S. Smithson; B. Meyer; W. Gross; H. Yamagata; H. Fujita; Takahiro Hanyu

doi:10.1109/IEEECONF44664.2019.9048700

A Design Framework for Invertible Logic

N. Onizawa, K. Nishino, S. Smithson, B. Meyer, W. Gross, H. Yamagata, H. Fujita, Takahiro Hanyu

Systems & Software Division

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Invertible logic using a probabilistic magnetoresistive device model has been recently presented that can operate in bidirectional ways and solve several problems quickly, such as factorization and combinational optimization. In this paper, we present a design framework for large-scale invertible logic circuits. Our approach makes use of linear programming to create a Hamiltonian library with the minimum number of nodes. In addition, as the device model is approximated based on stochastic computing in SystemVerilog, a faster simulation using the compiled SystemC binary is realized than a conventional SPICE-level simulation. We have evaluated our framework on designing invertible multipliers, which realizes almost 5 order-of-magnitude faster simulation than a conventional method.

Original language	English
Title of host publication	Conference Record - 53rd Asilomar Conference on Circuits, Systems and Computers, ACSSC 2019
Editors	Michael B. Matthews
Publisher	IEEE Computer Society
Pages	312-316
Number of pages	5
ISBN (Electronic)	9781728143002
DOIs	https://doi.org/10.1109/IEEECONF44664.2019.9048700
Publication status	Published - 2019 Nov
Event	53rd Asilomar Conference on Circuits, Systems and Computers, ACSSC 2019 - Pacific Grove, United States Duration: 2019 Nov 3 → 2019 Nov 6

Publication series

Name	Conference Record - Asilomar Conference on Signals, Systems and Computers
Volume	2019-November
ISSN (Print)	1058-6393

Conference

Conference	53rd Asilomar Conference on Circuits, Systems and Computers, ACSSC 2019
Country	United States
City	Pacific Grove
Period	19/11/3 → 19/11/6

Keywords

FPGA
Hamiltonian
Stochastic computing
SystemVer-ilog model

ASJC Scopus subject areas

Signal Processing
Computer Networks and Communications

Access to Document

10.1109/IEEECONF44664.2019.9048700

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Onizawa, N., Nishino, K., Smithson, S., Meyer, B., Gross, W., Yamagata, H., Fujita, H., & Hanyu, T. (2019). A Design Framework for Invertible Logic. In M. B. Matthews (Ed.), Conference Record - 53rd Asilomar Conference on Circuits, Systems and Computers, ACSSC 2019 (pp. 312-316). [9048700] (Conference Record - Asilomar Conference on Signals, Systems and Computers; Vol. 2019-November). IEEE Computer Society. https://doi.org/10.1109/IEEECONF44664.2019.9048700

A Design Framework for Invertible Logic. / Onizawa, N.; Nishino, K.; Smithson, S.; Meyer, B.; Gross, W.; Yamagata, H.; Fujita, H.; Hanyu, Takahiro.

Conference Record - 53rd Asilomar Conference on Circuits, Systems and Computers, ACSSC 2019. ed. / Michael B. Matthews. IEEE Computer Society, 2019. p. 312-316 9048700 (Conference Record - Asilomar Conference on Signals, Systems and Computers; Vol. 2019-November).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Onizawa, N, Nishino, K, Smithson, S, Meyer, B, Gross, W, Yamagata, H, Fujita, H & Hanyu, T 2019, A Design Framework for Invertible Logic. in MB Matthews (ed.), Conference Record - 53rd Asilomar Conference on Circuits, Systems and Computers, ACSSC 2019., 9048700, Conference Record - Asilomar Conference on Signals, Systems and Computers, vol. 2019-November, IEEE Computer Society, pp. 312-316, 53rd Asilomar Conference on Circuits, Systems and Computers, ACSSC 2019, Pacific Grove, United States, 19/11/3. https://doi.org/10.1109/IEEECONF44664.2019.9048700

Onizawa N, Nishino K, Smithson S, Meyer B, Gross W, Yamagata H et al. A Design Framework for Invertible Logic. In Matthews MB, editor, Conference Record - 53rd Asilomar Conference on Circuits, Systems and Computers, ACSSC 2019. IEEE Computer Society. 2019. p. 312-316. 9048700. (Conference Record - Asilomar Conference on Signals, Systems and Computers). https://doi.org/10.1109/IEEECONF44664.2019.9048700

Onizawa, N. ; Nishino, K. ; Smithson, S. ; Meyer, B. ; Gross, W. ; Yamagata, H. ; Fujita, H. ; Hanyu, Takahiro. / A Design Framework for Invertible Logic. Conference Record - 53rd Asilomar Conference on Circuits, Systems and Computers, ACSSC 2019. editor / Michael B. Matthews. IEEE Computer Society, 2019. pp. 312-316 (Conference Record - Asilomar Conference on Signals, Systems and Computers).

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