A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing

Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Ayuka Morioka, Yukihide Tsuji, Kunihiko Ishihara, Keiichi Tokutome, Sadahiko Miura, Shunsuke Fukami, Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno, Tadahiko Sugibayashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A delay circuit using four-terminal magnetic-random-access-memory (MRAM) devices was designed for power-efficient time-domain signal processing. A cell area of 6.4 μm2 was obtained using 90-nm CMOS/MRAM technologies. The basic operations to both store the data and control the delay time were confirmed on the fabricated test chips. In addition, we proposed a power-efficient neuromorphic core using the delay circuit.

Original languageEnglish
Title of host publication2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1588-1591
Number of pages4
ISBN (Print)9781479934324
DOIs
Publication statusPublished - 2014 Jan 1
Event2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia
Duration: 2014 Jun 12014 Jun 5

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

Other2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
CountryAustralia
CityMelbourne, VIC
Period14/6/114/6/5

Keywords

  • MRAM
  • delay circuit
  • restricted Boltzmann machine
  • spintronics
  • time-domain signal processing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing'. Together they form a unique fingerprint.

Cite this