A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing

Ryusuke Nebashi; Noboru Sakimura; Hiroaki Honjo; Ayuka Morioka; Yukihide Tsuji; Kunihiko Ishihara; Keiichi Tokutome; Sadahiko Miura; Shunsuke Fukami; Keizo Kinoshita; Takahiro Hanyu; Tetsuo Endoh; Naoki Kasai; Hideo Ohno; Tadahiko Sugibayashi

doi:10.1109/ISCAS.2014.6865453

A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing

Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Ayuka Morioka, Yukihide Tsuji, Kunihiko Ishihara, Keiichi Tokutome, Sadahiko Miura, Shunsuke Fukami, Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno, Tadahiko Sugibayashi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

A delay circuit using four-terminal magnetic-random-access-memory (MRAM) devices was designed for power-efficient time-domain signal processing. A cell area of 6.4 μm² was obtained using 90-nm CMOS/MRAM technologies. The basic operations to both store the data and control the delay time were confirmed on the fabricated test chips. In addition, we proposed a power-efficient neuromorphic core using the delay circuit.

Original language	English
Title of host publication	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1588-1591
Number of pages	4
ISBN (Print)	9781479934324
DOIs	https://doi.org/10.1109/ISCAS.2014.6865453
Publication status	Published - 2014 Jan 1
Event	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia Duration: 2014 Jun 1 → 2014 Jun 5

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Other

Other	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
Country	Australia
City	Melbourne, VIC
Period	14/6/1 → 14/6/5

Keywords

MRAM
delay circuit
restricted Boltzmann machine
spintronics
time-domain signal processing

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2014.6865453

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Nebashi, R., Sakimura, N., Honjo, H., Morioka, A., Tsuji, Y., Ishihara, K., Tokutome, K., Miura, S., Fukami, S., Kinoshita, K., Hanyu, T., Endoh, T., Kasai, N., Ohno, H., & Sugibayashi, T. (2014). A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. In 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 (pp. 1588-1591). [6865453] (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2014.6865453

A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. / Nebashi, Ryusuke; Sakimura, Noboru; Honjo, Hiroaki; Morioka, Ayuka; Tsuji, Yukihide; Ishihara, Kunihiko; Tokutome, Keiichi; Miura, Sadahiko ; Fukami, Shunsuke; Kinoshita, Keizo; Hanyu, Takahiro ; Endoh, Tetsuo; Kasai, Naoki; Ohno, Hideo; Sugibayashi, Tadahiko.

2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., 2014. p. 1588-1591 6865453 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Nebashi, R, Sakimura, N, Honjo, H, Morioka, A, Tsuji, Y, Ishihara, K, Tokutome, K, Miura, S , Fukami, S, Kinoshita, K, Hanyu, T , Endoh, T, Kasai, N, Ohno, H & Sugibayashi, T 2014, A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. in 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014., 6865453, Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., pp. 1588-1591, 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014, Melbourne, VIC, Australia, 14/6/1. https://doi.org/10.1109/ISCAS.2014.6865453

Nebashi R, Sakimura N, Honjo H, Morioka A, Tsuji Y, Ishihara K et al. A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. In 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc. 2014. p. 1588-1591. 6865453. (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2014.6865453

Nebashi, Ryusuke ; Sakimura, Noboru ; Honjo, Hiroaki ; Morioka, Ayuka ; Tsuji, Yukihide ; Ishihara, Kunihiko ; Tokutome, Keiichi ; Miura, Sadahiko ; Fukami, Shunsuke ; Kinoshita, Keizo ; Hanyu, Takahiro ; Endoh, Tetsuo ; Kasai, Naoki ; Ohno, Hideo ; Sugibayashi, Tadahiko. / A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., 2014. pp. 1588-1591 (Proceedings - IEEE International Symposium on Circuits and Systems).

@inproceedings{6c0c017cd6f044c79e97bb836a9082fb,

title = "A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing",

abstract = "A delay circuit using four-terminal magnetic-random-access-memory (MRAM) devices was designed for power-efficient time-domain signal processing. A cell area of 6.4 μm2 was obtained using 90-nm CMOS/MRAM technologies. The basic operations to both store the data and control the delay time were confirmed on the fabricated test chips. In addition, we proposed a power-efficient neuromorphic core using the delay circuit.",

keywords = "MRAM, delay circuit, restricted Boltzmann machine, spintronics, time-domain signal processing",

author = "Ryusuke Nebashi and Noboru Sakimura and Hiroaki Honjo and Ayuka Morioka and Yukihide Tsuji and Kunihiko Ishihara and Keiichi Tokutome and Sadahiko Miura and Shunsuke Fukami and Keizo Kinoshita and Takahiro Hanyu and Tetsuo Endoh and Naoki Kasai and Hideo Ohno and Tadahiko Sugibayashi",

year = "2014",

month = jan,

day = "1",

doi = "10.1109/ISCAS.2014.6865453",

language = "English",

isbn = "9781479934324",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1588--1591",

booktitle = "2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014",

note = "2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 ; Conference date: 01-06-2014 Through 05-06-2014",

}

TY - GEN

T1 - A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing

AU - Nebashi, Ryusuke

AU - Sakimura, Noboru

AU - Honjo, Hiroaki

AU - Morioka, Ayuka

AU - Tsuji, Yukihide

AU - Ishihara, Kunihiko

AU - Tokutome, Keiichi

AU - Miura, Sadahiko

AU - Fukami, Shunsuke

AU - Kinoshita, Keizo

AU - Hanyu, Takahiro

AU - Endoh, Tetsuo

AU - Kasai, Naoki

AU - Ohno, Hideo

AU - Sugibayashi, Tadahiko

PY - 2014/1/1

Y1 - 2014/1/1

N2 - A delay circuit using four-terminal magnetic-random-access-memory (MRAM) devices was designed for power-efficient time-domain signal processing. A cell area of 6.4 μm2 was obtained using 90-nm CMOS/MRAM technologies. The basic operations to both store the data and control the delay time were confirmed on the fabricated test chips. In addition, we proposed a power-efficient neuromorphic core using the delay circuit.

AB - A delay circuit using four-terminal magnetic-random-access-memory (MRAM) devices was designed for power-efficient time-domain signal processing. A cell area of 6.4 μm2 was obtained using 90-nm CMOS/MRAM technologies. The basic operations to both store the data and control the delay time were confirmed on the fabricated test chips. In addition, we proposed a power-efficient neuromorphic core using the delay circuit.

KW - MRAM

KW - delay circuit

KW - restricted Boltzmann machine

KW - spintronics

KW - time-domain signal processing

UR - http://www.scopus.com/inward/record.url?scp=84907409270&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84907409270&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2014.6865453

DO - 10.1109/ISCAS.2014.6865453

M3 - Conference contribution

AN - SCOPUS:84907409270

SN - 9781479934324

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 1588

EP - 1591

BT - 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014

Y2 - 1 June 2014 through 5 June 2014

ER -