A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing

Ryusuke Nebashi; Noboru Sakimura; Hiroaki Honjo; Ayuka Morioka; Yukihide Tsuji; Kunihiko Ishihara; Keiichi Tokutome; Sadahiko Miura; Shunsuke Fukami; Keizo Kinoshita; Takahiro Hanyu; Tetsuo Endoh; Naoki Kasai; Hideo Ohno; Tadahiko Sugibayashi

doi:10.1109/ISCAS.2014.6865453

A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing

Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Ayuka Morioka, Yukihide Tsuji, Kunihiko Ishihara, Keiichi Tokutome, Sadahiko Miura, Shunsuke Fukami, Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno, Tadahiko Sugibayashi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

A delay circuit using four-terminal magnetic-random-access-memory (MRAM) devices was designed for power-efficient time-domain signal processing. A cell area of 6.4 μm² was obtained using 90-nm CMOS/MRAM technologies. The basic operations to both store the data and control the delay time were confirmed on the fabricated test chips. In addition, we proposed a power-efficient neuromorphic core using the delay circuit.

Original language	English
Title of host publication	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1588-1591
Number of pages	4
ISBN (Print)	9781479934324
DOIs	https://doi.org/10.1109/ISCAS.2014.6865453
Publication status	Published - 2014 Jan 1
Event	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia Duration: 2014 Jun 1 → 2014 Jun 5

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Other

Other	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
Country/Territory	Australia
City	Melbourne, VIC
Period	14/6/1 → 14/6/5

Keywords

MRAM
delay circuit
restricted Boltzmann machine
spintronics
time-domain signal processing

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2014.6865453

Cite this

Nebashi, R., Sakimura, N., Honjo, H., Morioka, A., Tsuji, Y., Ishihara, K., Tokutome, K., Miura, S., Fukami, S., Kinoshita, K., Hanyu, T., Endoh, T., Kasai, N., Ohno, H., & Sugibayashi, T. (2014). A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. In 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 (pp. 1588-1591). [6865453] (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2014.6865453

A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. / Nebashi, Ryusuke; Sakimura, Noboru; Honjo, Hiroaki; Morioka, Ayuka; Tsuji, Yukihide; Ishihara, Kunihiko; Tokutome, Keiichi; Miura, Sadahiko ; Fukami, Shunsuke; Kinoshita, Keizo; Hanyu, Takahiro ; Endoh, Tetsuo; Kasai, Naoki; Ohno, Hideo; Sugibayashi, Tadahiko.

2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., 2014. p. 1588-1591 6865453 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Nebashi, R, Sakimura, N, Honjo, H, Morioka, A, Tsuji, Y, Ishihara, K, Tokutome, K, Miura, S , Fukami, S, Kinoshita, K, Hanyu, T , Endoh, T, Kasai, N, Ohno, H & Sugibayashi, T 2014, A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. in 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014., 6865453, Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., pp. 1588-1591, 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014, Melbourne, VIC, Australia, 14/6/1. https://doi.org/10.1109/ISCAS.2014.6865453

Nebashi R, Sakimura N, Honjo H, Morioka A, Tsuji Y, Ishihara K et al. A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. In 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc. 2014. p. 1588-1591. 6865453. (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2014.6865453

Nebashi, Ryusuke ; Sakimura, Noboru ; Honjo, Hiroaki ; Morioka, Ayuka ; Tsuji, Yukihide ; Ishihara, Kunihiko ; Tokutome, Keiichi ; Miura, Sadahiko ; Fukami, Shunsuke ; Kinoshita, Keizo ; Hanyu, Takahiro ; Endoh, Tetsuo ; Kasai, Naoki ; Ohno, Hideo ; Sugibayashi, Tadahiko. / A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014. Institute of Electrical and Electronics Engineers Inc., 2014. pp. 1588-1591 (Proceedings - IEEE International Symposium on Circuits and Systems).

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A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing

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