A convolutional neural network VLSI for image recognition using merged/mixed analog-digital architecture

Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata

Research output: Contribution to journalConference articlepeer-review

20 Citations (Scopus)


Hierarchical convolutional neural networks are a well-known robust image-recognition model. In order to apply this model to robot vision or various intelligent vision systems, its VLSI implementation with high performance and low power consumption is required. This paper proposes a convolutional network VLSI architecture using a hybrid approach composed of pulse-width modulation (PWM) and digital circuits. We call this approach merged/mixed analog-digital architecture. The VLSI includes PWM neuron circuits, PWM/digital converters, digital adder-subtracters, and digital memory. We have designed and fabricated a VLSI chip by using a 0.35 μn CMOS process. The VLSI chip can perform 6-bit precision convolution calculations for an image of 100x100 pixels with a receptive field area of up to 20x20 pixels within 5 ms, which means a performance of 2 GOPS. Power consumption of PWM neuron circuits is estimated to be 20 mW. We have verified successful operations using a fabricated VLSI chip.

Original languageEnglish
Pages (from-to)169-175
Number of pages7
JournalLecture Notes in Artificial Intelligence (Subseries of Lecture Notes in Computer Science)
Volume2774 PART 2
Publication statusPublished - 2003
Externally publishedYes
Event7th International Conference, KES 2003 - Oxford, United Kingdom
Duration: 2003 Sep 32003 Sep 5

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)


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