A convolutional neural network VLSI architecture using sorting model for reducing multiply-and-accumulation operations

Osamu Nomura, Takashi Morie, Masakazu Matsugu, Atsushi Iwata

Research output: Contribution to journalConference articlepeer-review

1 Citation (Scopus)

Abstract

Hierarchical convolutional neural networks are a well-known robust image-recognition model. In order to apply this model to robot vision or various intelligent real-time vision systems, its VLSI implementation is essential. This paper proposes a new algorithm for reducing multiply-and-accumulation operation by sorting neuron outputs by magnitude. We also propose a VLSI architecture based on this algorithm. We have designed and fabricated a sorting LSI by using a 0.35 μm CMOS process. We have verified successful sorting operations at 100 MHz clock cycle by circuit simulation.

Original languageEnglish
Pages (from-to)1006-1014
Number of pages9
JournalLecture Notes in Computer Science
Volume3612
Issue numberPART III
DOIs
Publication statusPublished - 2005
Externally publishedYes
EventFirst International Conference on Natural Computation, ICNC 2005 - Changsha, China
Duration: 2005 Aug 272005 Aug 29

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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