A convolutional neural network VLSI architecture using sorting model for reducing multiply-and-accumulation operations

Osamu Nomura; Takashi Morie; Masakazu Matsugu; Atsushi Iwata

doi:10.1007/11539902_129

A convolutional neural network VLSI architecture using sorting model for reducing multiply-and-accumulation operations

Osamu Nomura, Takashi Morie, Masakazu Matsugu, Atsushi Iwata

Research output: Contribution to journal › Conference article › peer-review

1 Citation (Scopus)

Abstract

Hierarchical convolutional neural networks are a well-known robust image-recognition model. In order to apply this model to robot vision or various intelligent real-time vision systems, its VLSI implementation is essential. This paper proposes a new algorithm for reducing multiply-and-accumulation operation by sorting neuron outputs by magnitude. We also propose a VLSI architecture based on this algorithm. We have designed and fabricated a sorting LSI by using a 0.35 μm CMOS process. We have verified successful sorting operations at 100 MHz clock cycle by circuit simulation.

Original language	English
Pages (from-to)	1006-1014
Number of pages	9
Journal	Lecture Notes in Computer Science
Volume	3612
Issue number	PART III
DOIs	https://doi.org/10.1007/11539902_129
Publication status	Published - 2005
Externally published	Yes
Event	First International Conference on Natural Computation, ICNC 2005 - Changsha, China Duration: 2005 Aug 27 → 2005 Aug 29

ASJC Scopus subject areas

Theoretical Computer Science
Computer Science(all)

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10.1007/11539902_129

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title = "A convolutional neural network VLSI architecture using sorting model for reducing multiply-and-accumulation operations",

abstract = "Hierarchical convolutional neural networks are a well-known robust image-recognition model. In order to apply this model to robot vision or various intelligent real-time vision systems, its VLSI implementation is essential. This paper proposes a new algorithm for reducing multiply-and-accumulation operation by sorting neuron outputs by magnitude. We also propose a VLSI architecture based on this algorithm. We have designed and fabricated a sorting LSI by using a 0.35 μm CMOS process. We have verified successful sorting operations at 100 MHz clock cycle by circuit simulation.",

author = "Osamu Nomura and Takashi Morie and Masakazu Matsugu and Atsushi Iwata",

year = "2005",

doi = "10.1007/11539902_129",

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journal = "Lecture Notes in Computer Science",

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AU - Nomura, Osamu

AU - Morie, Takashi

AU - Matsugu, Masakazu

AU - Iwata, Atsushi

PY - 2005

Y1 - 2005

N2 - Hierarchical convolutional neural networks are a well-known robust image-recognition model. In order to apply this model to robot vision or various intelligent real-time vision systems, its VLSI implementation is essential. This paper proposes a new algorithm for reducing multiply-and-accumulation operation by sorting neuron outputs by magnitude. We also propose a VLSI architecture based on this algorithm. We have designed and fabricated a sorting LSI by using a 0.35 μm CMOS process. We have verified successful sorting operations at 100 MHz clock cycle by circuit simulation.

AB - Hierarchical convolutional neural networks are a well-known robust image-recognition model. In order to apply this model to robot vision or various intelligent real-time vision systems, its VLSI implementation is essential. This paper proposes a new algorithm for reducing multiply-and-accumulation operation by sorting neuron outputs by magnitude. We also propose a VLSI architecture based on this algorithm. We have designed and fabricated a sorting LSI by using a 0.35 μm CMOS process. We have verified successful sorting operations at 100 MHz clock cycle by circuit simulation.

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JO - Lecture Notes in Computer Science

JF - Lecture Notes in Computer Science

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ER -

A convolutional neural network VLSI architecture using sorting model for reducing multiply-and-accumulation operations

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