A configurable on-chip glitchy-clock generator for fault injection experiments

Sho Endo, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh

Research output: Contribution to journalArticlepeer-review

8 Citations (Scopus)

Abstract

This paper presents a glitchy-clock generator integrated in FPGA for evaluating fault injection attacks and their countermeasures on cryptographic modules. The proposed generator exploits clock management capabilities, which are common in modern FPGAs, to generate clock signal with temporal voltage spike. The shape and timing of the glitchyclock cycle are configurable at run time. The proposed generator can be embedded in a single FPGA without any external instrument (e.g., a pulse generator and a variable power supply). Such integration enables reliable and reproducible fault injection experiments. In this paper, we examine the characteristics of the proposed generator through experiments on Sidechannel Attack Standard Evaluation Board (SASEBO). The result shows that the timing of the glitches can be controlled at the step of about 0.17 ns. We also demonstrate its application to the safe-error attack against an RSA processor.

Original languageEnglish
Pages (from-to)263-266
Number of pages4
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE-95-A
Issue number1
DOIs
Publication statusPublished - 2012 Jan

Keywords

  • Clock glitch
  • Faulty injection attacks
  • RSA
  • Safe-error attack

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

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