A compact space and efficient drain current design for multipillar vertical MOSFETs

Koji Sakui, Tetsuo Endoh

Research output: Contribution to journalArticlepeer-review

9 Citations (Scopus)

Abstract

In the vertical MOSFET, due to its device structure, the bottom of its silicon pillar has a certain resistance because there is a diffused silicon wiring area in the bottom. Thereby, this resistance becomes large in the case of the multipillar transistors and also shows asymmetric characteristics between the top and bottom nodes of the pillar. This paper is devoted to examining this resistance for the multipillar vertical MOSFETs and proposing a compact design, which can suppress the resistance influences, attain a large drain current, and achieve a higher circuit performance.

Original languageEnglish
Article number5491144
Pages (from-to)1768-1773
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume57
Issue number8
DOIs
Publication statusPublished - 2010 Aug

Keywords

  • Bottom node resistance
  • multipillar MOSFETS
  • vertical MOSFET

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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