TY - GEN
T1 - A compact soft-error tolerant asynchronous TCAM based on a transistor/magnetic-tunnel-junction hybrid dual-rail word structure
AU - Onizawa, Naoya
AU - Matsunaga, Shoun
AU - Hanyu, Takahiro
PY - 2014/1/1
Y1 - 2014/1/1
N2 - This paper introduces a soft-error tolerant asynchronous ternary content-addressable memory (TCAM) based on a transistor/magnetic-tunnel-junction (MTJ) hybrid structure. An MTJ device that is often used for a non-volatile memory stores one-bit information as a resistance whose value is robust against alpha particle and atmosphere neutron strikes, which significantly lower the probability of single-event upsets (SEUs). The TCAM is also robust against delay variations caused by single-event transients (SETs) as it is designed based on four-phase dual-rail encoding realized using complementary NAND and NOR-type word circuits. The dual-rail TCAM cell is compactly designed using 20 transistors (20T) and 4 MTJ devices stacked on a CMOS layer as opposed to a single-rail 24T TCAM cell that consists of soft-error tolerant storage elements. In addition, soft errors can be detected using the dual-rail signals. As a design example, a 256-word x 64-bit TCAM is designed under a 90 nm CMOS/MTJ technology and is evaluated with a collected charge caused by a particle strike, which induces the SET and hence the delay variation. The proposed TCAM properly operates under the delay variation, while achieving comparable performance to a synchronous single-rail TCAM in which an up to 25% timing error occurs.
AB - This paper introduces a soft-error tolerant asynchronous ternary content-addressable memory (TCAM) based on a transistor/magnetic-tunnel-junction (MTJ) hybrid structure. An MTJ device that is often used for a non-volatile memory stores one-bit information as a resistance whose value is robust against alpha particle and atmosphere neutron strikes, which significantly lower the probability of single-event upsets (SEUs). The TCAM is also robust against delay variations caused by single-event transients (SETs) as it is designed based on four-phase dual-rail encoding realized using complementary NAND and NOR-type word circuits. The dual-rail TCAM cell is compactly designed using 20 transistors (20T) and 4 MTJ devices stacked on a CMOS layer as opposed to a single-rail 24T TCAM cell that consists of soft-error tolerant storage elements. In addition, soft errors can be detected using the dual-rail signals. As a design example, a 256-word x 64-bit TCAM is designed under a 90 nm CMOS/MTJ technology and is evaluated with a collected charge caused by a particle strike, which induces the SET and hence the delay variation. The proposed TCAM properly operates under the delay variation, while achieving comparable performance to a synchronous single-rail TCAM in which an up to 25% timing error occurs.
KW - Single-event upset (SEU)
KW - content-addressable memory
KW - magnetic-tunnel-junction (MTJ)
KW - single-event transient (SET)
UR - http://www.scopus.com/inward/record.url?scp=84903852588&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84903852588&partnerID=8YFLogxK
U2 - 10.1109/ASYNC.2014.9
DO - 10.1109/ASYNC.2014.9
M3 - Conference contribution
AN - SCOPUS:84903852588
SN - 9781479937899
T3 - Proceedings - International Symposium on Asynchronous Circuits and Systems
SP - 1
EP - 8
BT - Proceedings - 20th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2014
PB - IEEE Computer Society
T2 - 20th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2014
Y2 - 12 May 2014 through 14 May 2014
ER -