A cache partitioning mechanism to protect shared data for CMPs

Masayuki Sato, Shin Nishimura, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The last-level cache (LLC) of a modern chip-multiprocessor (CMP) keeps two kinds of data: shared data accessed by multiple cores and private data accessed by only one core. Although the former are likely to have a larger performance impact than the latter, the LLC manages both of those data in the same fashion. To realize a highly efficient execution on a CMP, this paper proposes a cache partitioning mechanism to protect shared data from excessive eviction. The evaluation results show that the proposed mechanism improves the performance by up to 76% and by 8% on average at a cost of less than 2% of the LLC hardware.

Original languageEnglish
Title of host publication19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509013869
DOIs
Publication statusPublished - 2016 Jul 5
Event19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 - Yokohama, Japan
Duration: 2016 Apr 202016 Apr 22

Publication series

Name19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 - Proceedings

Other

Other19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016
CountryJapan
CityYokohama
Period16/4/2016/4/22

Keywords

  • cache memory
  • cache partitioning
  • chip-multiprocessor
  • shared data

ASJC Scopus subject areas

  • Hardware and Architecture

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