An ADC design with a hierarchical double correlated double sampling for a three-dimensional (3-D) stacked CMOS image sensor is presented in this paper. To realize high speed, high resolution, and high sensitivity, we have proposed a blockparallel signal processing with 3-D structure. The block-parallel analog signal processing elements which compose CMOS image sensor, correlated double sampling (CDS) with programmable gain amplifier (PGA) array, and analog-to-digital converter (ADC) array. Spatial noise is the main contributor of image distortion in CMOS image sensor. Fixed pattern noise (FPN) does not change with time, and causes fixed distortion pattern on the image, hence FPN correction is especially challenging in the high speed CMOS image sensor. In the proposed sensor system, FPN of pixel output is removed by analog CDS. The digital CDS proposed in this paper is used to eliminate FPN caused by the device variation of analog circuits. The proposed ADC was designed with 90-nm CMOS technology. The proposed ADC with digital CDS occupies a very small circuit area of 160X160μm2. The block-parallel ADC performance is characterized through differential nonlinearity (DNL) and integral nonlinearity (INL) measurements. The DNL is within -1.49/+1.89 LSB, and the INL is -1.92/+2.44 LSB, respectively. FPN is reduced to the range of ±1LSB by using proposed hierarchical double CDS function.