A bit-serial reconfigurable VLSI based on a multiple-valued X-net data transfer scheme

Xu Bai, Michitaka Kameyama

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)

Abstract

A multiple-valued data transfer scheme using X-net is proposed to realize a compact bit-serial reconfigurable VLSI (BS-RVLSI). In the multiple-valued data transfer scheme using X-net, two binary data can be transferred from two adjacent cells to one common adjacent cell simultaneously at each 'X' intersection. One cell composed of a logic block and a switch block is connected to four adjacent cross points by four onebit switches so that the complexity of the switch block is reduced to 50% in comparison with the cell of a BS-RVLSI using an eight nearest-neighbor mesh network (8-NNM). In the logic block, threshold logic circuits are used to perform threshold operations, and then their binary dual-rail voltage outputs enter a binary logic module which can be programmed to realize an arbitrary two-variable binary function or a bit-serial adder. As a result, the configuration memory count and transistor count of the proposed multiplevalued cell are reduced to 34% and 58%, respectively, in comparison with those of an equivalent CMOS cell. Moreover, its power consumption for an arbitrary 2-variable binary function becomes 67% at 800MHz under the condition of the same delay time.

Original languageEnglish
Pages (from-to)1449-1456
Number of pages8
JournalIEICE Transactions on Information and Systems
VolumeE96-D
Issue number7
DOIs
Publication statusPublished - 2013 Jul

Keywords

  • Fine-grain reconfigurable VLSI
  • MOS current-mode logic
  • Multiple-valued current-mode logic
  • Multiple-valued data transfer scheme
  • X-net

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence

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