TY - JOUR
T1 - A 64-Mb Chain FeRAM with quad BL architecture and 200 MB/s burst mode
AU - Hoya, Katsuhiko
AU - Takashima, Daisaburo
AU - Shiratake, Shinichiro
AU - Ogiwara, Ryu
AU - Miyakawa, Tadashi
AU - Shiga, Hidehiro
AU - Doumae, Sumiko M.
AU - Ohtsuki, Sumito
AU - Kumura, Yoshinori
AU - Shuto, Susumu
AU - Ozaki, Tohru
AU - Yamakawa, Koji
AU - Kunishima, Iwao
AU - Nitayama, Akihiro
AU - Fujii, Shuso
PY - 2010/12/1
Y1 - 2010/12/1
N2 - A 64-Mb chain ferroelectric RAM (chainFeRAM) is fabricated using 130-nm 3-metal CMOS technology. A newly developed quad bitline architecture, which combines folded bitline configuration with shield bitline scheme, eliminates bitline-bitline (BL-BL) coupling noise. The quad bitline architecture also reduces the number of sense amplifiers and activated bitlines, resulting in the reduction of die size by 6.5% and cell array power consumption by 28%. Fast read/write of 60-ns cycle time as well as reliability improvement are realized by two high-speed error checking and correcting (ECC) techniques: 1) fast pre-parity calculation ECC sequence and 2) all-"0"-write-before-data- write scheme. Moreover, among nonvolatile memories reported so far, the 64 Mb chain FeRAM has achieved the highest read/write bandwidth of 200 MB/s with ECC. The chip size is 87.5 mm2 with average cell size of 0.7191 μm 2.
AB - A 64-Mb chain ferroelectric RAM (chainFeRAM) is fabricated using 130-nm 3-metal CMOS technology. A newly developed quad bitline architecture, which combines folded bitline configuration with shield bitline scheme, eliminates bitline-bitline (BL-BL) coupling noise. The quad bitline architecture also reduces the number of sense amplifiers and activated bitlines, resulting in the reduction of die size by 6.5% and cell array power consumption by 28%. Fast read/write of 60-ns cycle time as well as reliability improvement are realized by two high-speed error checking and correcting (ECC) techniques: 1) fast pre-parity calculation ECC sequence and 2) all-"0"-write-before-data- write scheme. Moreover, among nonvolatile memories reported so far, the 64 Mb chain FeRAM has achieved the highest read/write bandwidth of 200 MB/s with ECC. The chip size is 87.5 mm2 with average cell size of 0.7191 μm 2.
KW - Burst mode
KW - ferroelectric memory
KW - nonvolatile memory
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U2 - 10.1109/TVLSI.2009.2034380
DO - 10.1109/TVLSI.2009.2034380
M3 - Article
AN - SCOPUS:78649496253
VL - 18
SP - 1745
EP - 1752
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 12
M1 - 5339093
ER -