A 64-Mb Chain FeRAM with quad BL architecture and 200 MB/s burst mode

Katsuhiko Hoya; Daisaburo Takashima; Shinichiro Shiratake; Ryu Ogiwara; Tadashi Miyakawa; Hidehiro Shiga; Sumiko M. Doumae; Sumito Ohtsuki; Yoshinori Kumura; Susumu Shuto; Tohru Ozaki; Koji Yamakawa; Iwao Kunishima; Akihiro Nitayama; Shuso Fujii

doi:10.1109/TVLSI.2009.2034380

A 64-Mb Chain FeRAM with quad BL architecture and 200 MB/s burst mode

Katsuhiko Hoya, Daisaburo Takashima, Shinichiro Shiratake, Ryu Ogiwara, Tadashi Miyakawa, Hidehiro Shiga, Sumiko M. Doumae, Sumito Ohtsuki, Yoshinori Kumura, Susumu Shuto, Tohru Ozaki, Koji Yamakawa, Iwao Kunishima, Akihiro Nitayama, Shuso Fujii

Center for Innovative Integrated Electronic Systems (CIES)

Research output: Contribution to journal › Article › peer-review

13 Citations (Scopus)

Abstract

A 64-Mb chain ferroelectric RAM (chainFeRAM) is fabricated using 130-nm 3-metal CMOS technology. A newly developed quad bitline architecture, which combines folded bitline configuration with shield bitline scheme, eliminates bitline-bitline (BL-BL) coupling noise. The quad bitline architecture also reduces the number of sense amplifiers and activated bitlines, resulting in the reduction of die size by 6.5% and cell array power consumption by 28%. Fast read/write of 60-ns cycle time as well as reliability improvement are realized by two high-speed error checking and correcting (ECC) techniques: 1) fast pre-parity calculation ECC sequence and 2) all-"0"-write-before-data- write scheme. Moreover, among nonvolatile memories reported so far, the 64 Mb chain FeRAM has achieved the highest read/write bandwidth of 200 MB/s with ECC. The chip size is 87.5 mm² with average cell size of 0.7191 μm ².

Original language	English
Article number	5339093
Pages (from-to)	1745-1752
Number of pages	8
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	18
Issue number	12
DOIs	https://doi.org/10.1109/TVLSI.2009.2034380
Publication status	Published - 2010 Dec 1

Keywords

Burst mode
ferroelectric memory
nonvolatile memory

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/TVLSI.2009.2034380

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Hoya, K., Takashima, D., Shiratake, S., Ogiwara, R., Miyakawa, T., Shiga, H., Doumae, S. M., Ohtsuki, S., Kumura, Y., Shuto, S., Ozaki, T., Yamakawa, K., Kunishima, I., Nitayama, A., & Fujii, S. (2010). A 64-Mb Chain FeRAM with quad BL architecture and 200 MB/s burst mode. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(12), 1745-1752. [5339093]. https://doi.org/10.1109/TVLSI.2009.2034380

Hoya, K, Takashima, D, Shiratake, S, Ogiwara, R, Miyakawa, T, Shiga, H, Doumae, SM, Ohtsuki, S, Kumura, Y, Shuto, S, Ozaki, T, Yamakawa, K, Kunishima, I, Nitayama, A & Fujii, S 2010, 'A 64-Mb Chain FeRAM with quad BL architecture and 200 MB/s burst mode', IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 12, 5339093, pp. 1745-1752. https://doi.org/10.1109/TVLSI.2009.2034380

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AU - Miyakawa, Tadashi

AU - Shiga, Hidehiro

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AU - Kumura, Yoshinori

AU - Shuto, Susumu

AU - Ozaki, Tohru

AU - Yamakawa, Koji

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N2 - A 64-Mb chain ferroelectric RAM (chainFeRAM) is fabricated using 130-nm 3-metal CMOS technology. A newly developed quad bitline architecture, which combines folded bitline configuration with shield bitline scheme, eliminates bitline-bitline (BL-BL) coupling noise. The quad bitline architecture also reduces the number of sense amplifiers and activated bitlines, resulting in the reduction of die size by 6.5% and cell array power consumption by 28%. Fast read/write of 60-ns cycle time as well as reliability improvement are realized by two high-speed error checking and correcting (ECC) techniques: 1) fast pre-parity calculation ECC sequence and 2) all-"0"-write-before-data- write scheme. Moreover, among nonvolatile memories reported so far, the 64 Mb chain FeRAM has achieved the highest read/write bandwidth of 200 MB/s with ECC. The chip size is 87.5 mm2 with average cell size of 0.7191 μm 2.

AB - A 64-Mb chain ferroelectric RAM (chainFeRAM) is fabricated using 130-nm 3-metal CMOS technology. A newly developed quad bitline architecture, which combines folded bitline configuration with shield bitline scheme, eliminates bitline-bitline (BL-BL) coupling noise. The quad bitline architecture also reduces the number of sense amplifiers and activated bitlines, resulting in the reduction of die size by 6.5% and cell array power consumption by 28%. Fast read/write of 60-ns cycle time as well as reliability improvement are realized by two high-speed error checking and correcting (ECC) techniques: 1) fast pre-parity calculation ECC sequence and 2) all-"0"-write-before-data- write scheme. Moreover, among nonvolatile memories reported so far, the 64 Mb chain FeRAM has achieved the highest read/write bandwidth of 200 MB/s with ECC. The chip size is 87.5 mm2 with average cell size of 0.7191 μm 2.

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A 64-Mb Chain FeRAM with quad BL architecture and 200 MB/s burst mode

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Keywords

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