TY - GEN
T1 - A 60nm NOR flash memory cell technology utilizing back bias assisted band-to-band tunneling induced hot-electron injection (B4-Flash)
AU - Shukuri, Shoji
AU - Ajika, Natsuo
AU - Mihara, Masaaki
AU - Kobayashi, Kazuo
AU - Endoh, Tetsuo
AU - Nakashima, Moriyoshi
PY - 2006/12/1
Y1 - 2006/12/1
N2 - A p-channel SONOS flash memory cell technology, which provides excellent scalability and high programming efficiency for NOR architecture, has been developed. The cells named B4-Flash utilizing novel Back Bias assisted Band-to-Band tunneling induced hot-electron (B4-HE) injection is proposed. By applying a moderate back bias to the cell during programming, the bit-line voltage can be reduced below the supply voltage, 1.8V. Resulting that the B4-Flash, applicable to NOR architecture, achieves the gate length of 60nm, for the first time. Basic operation of the 50nm B4-Flash cell is also confirmed. Proposed B4-HE injection scheme realizes not only extreme scalability but also high programming efficiency for NOR type cell.
AB - A p-channel SONOS flash memory cell technology, which provides excellent scalability and high programming efficiency for NOR architecture, has been developed. The cells named B4-Flash utilizing novel Back Bias assisted Band-to-Band tunneling induced hot-electron (B4-HE) injection is proposed. By applying a moderate back bias to the cell during programming, the bit-line voltage can be reduced below the supply voltage, 1.8V. Resulting that the B4-Flash, applicable to NOR architecture, achieves the gate length of 60nm, for the first time. Basic operation of the 50nm B4-Flash cell is also confirmed. Proposed B4-HE injection scheme realizes not only extreme scalability but also high programming efficiency for NOR type cell.
UR - http://www.scopus.com/inward/record.url?scp=41149151859&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=41149151859&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:41149151859
SN - 1424400058
SN - 9781424400058
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - 15
EP - 16
BT - 2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers
T2 - 2006 Symposium on VLSI Technology, VLSIT
Y2 - 13 June 2006 through 15 June 2006
ER -