A 60nm NOR flash memory cell technology utilizing back bias assisted band-to-band tunneling induced hot-electron injection (B4-Flash)

Shoji Shukuri, Natsuo Ajika, Masaaki Mihara, Kazuo Kobayashi, Tetsuo Endoh, Moriyoshi Nakashima

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

A p-channel SONOS flash memory cell technology, which provides excellent scalability and high programming efficiency for NOR architecture, has been developed. The cells named B4-Flash utilizing novel Back Bias assisted Band-to-Band tunneling induced hot-electron (B4-HE) injection is proposed. By applying a moderate back bias to the cell during programming, the bit-line voltage can be reduced below the supply voltage, 1.8V. Resulting that the B4-Flash, applicable to NOR architecture, achieves the gate length of 60nm, for the first time. Basic operation of the 50nm B4-Flash cell is also confirmed. Proposed B4-HE injection scheme realizes not only extreme scalability but also high programming efficiency for NOR type cell.

Original languageEnglish
Title of host publication2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers
Pages15-16
Number of pages2
Publication statusPublished - 2006 Dec 1
Event2006 Symposium on VLSI Technology, VLSIT - Honolulu, HI, United States
Duration: 2006 Jun 132006 Jun 15

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Other

Other2006 Symposium on VLSI Technology, VLSIT
CountryUnited States
CityHonolulu, HI
Period06/6/1306/6/15

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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