A 60nm NOR flash memory cell technology utilizing back bias assisted band-to-band tunneling induced hot-electron injection (B4-Flash)

Shoji Shukuri; Natsuo Ajika; Masaaki Mihara; Kazuo Kobayashi; Tetsuo Endoh; Moriyoshi Nakashima

A 60nm NOR flash memory cell technology utilizing back bias assisted band-to-band tunneling induced hot-electron injection (B4-Flash)

Shoji Shukuri, Natsuo Ajika, Masaaki Mihara, Kazuo Kobayashi, Tetsuo Endoh, Moriyoshi Nakashima

ENG - Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

12 Citations (Scopus)

Abstract

A p-channel SONOS flash memory cell technology, which provides excellent scalability and high programming efficiency for NOR architecture, has been developed. The cells named B4-Flash utilizing novel Back Bias assisted Band-to-Band tunneling induced hot-electron (B4-HE) injection is proposed. By applying a moderate back bias to the cell during programming, the bit-line voltage can be reduced below the supply voltage, 1.8V. Resulting that the B4-Flash, applicable to NOR architecture, achieves the gate length of 60nm, for the first time. Basic operation of the 50nm B4-Flash cell is also confirmed. Proposed B4-HE injection scheme realizes not only extreme scalability but also high programming efficiency for NOR type cell.

Original language	English
Title of host publication	2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers
Pages	15-16
Number of pages	2
Publication status	Published - 2006 Dec 1
Event	2006 Symposium on VLSI Technology, VLSIT - Honolulu, HI, United States Duration: 2006 Jun 13 → 2006 Jun 15

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Other

Other	2006 Symposium on VLSI Technology, VLSIT
Country/Territory	United States
City	Honolulu, HI
Period	06/6/13 → 06/6/15

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

Shukuri, S., Ajika, N., Mihara, M., Kobayashi, K., Endoh, T., & Nakashima, M. (2006). A 60nm NOR flash memory cell technology utilizing back bias assisted band-to-band tunneling induced hot-electron injection (B4-Flash). In 2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers (pp. 15-16). [1705194] (Digest of Technical Papers - Symposium on VLSI Technology).

A 60nm NOR flash memory cell technology utilizing back bias assisted band-to-band tunneling induced hot-electron injection (B4-Flash). / Shukuri, Shoji; Ajika, Natsuo; Mihara, Masaaki; Kobayashi, Kazuo; Endoh, Tetsuo; Nakashima, Moriyoshi.

2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers. 2006. p. 15-16 1705194 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Shukuri, S, Ajika, N, Mihara, M, Kobayashi, K, Endoh, T & Nakashima, M 2006, A 60nm NOR flash memory cell technology utilizing back bias assisted band-to-band tunneling induced hot-electron injection (B4-Flash). in 2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers., 1705194, Digest of Technical Papers - Symposium on VLSI Technology, pp. 15-16, 2006 Symposium on VLSI Technology, VLSIT, Honolulu, HI, United States, 06/6/13.

Shukuri, Shoji ; Ajika, Natsuo ; Mihara, Masaaki ; Kobayashi, Kazuo ; Endoh, Tetsuo ; Nakashima, Moriyoshi. / A 60nm NOR flash memory cell technology utilizing back bias assisted band-to-band tunneling induced hot-electron injection (B4-Flash). 2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers. 2006. pp. 15-16 (Digest of Technical Papers - Symposium on VLSI Technology).

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abstract = "A p-channel SONOS flash memory cell technology, which provides excellent scalability and high programming efficiency for NOR architecture, has been developed. The cells named B4-Flash utilizing novel Back Bias assisted Band-to-Band tunneling induced hot-electron (B4-HE) injection is proposed. By applying a moderate back bias to the cell during programming, the bit-line voltage can be reduced below the supply voltage, 1.8V. Resulting that the B4-Flash, applicable to NOR architecture, achieves the gate length of 60nm, for the first time. Basic operation of the 50nm B4-Flash cell is also confirmed. Proposed B4-HE injection scheme realizes not only extreme scalability but also high programming efficiency for NOR type cell.",

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A 60nm NOR flash memory cell technology utilizing back bias assisted band-to-band tunneling induced hot-electron injection (B4-Flash)

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