This paper proposes three circuit technologies For achieving mega-bit-class nonvolatile ferroelectric RAM's (NVFRAM's). The proposed nondriven cell plate line write/read scheme (NDP scheme) accomplishes fast write/read operation equivalent to that of DRAM's. Problems and countermeasures in introducing this scheme into NVFRAM's are also discussed. A proposed optimized CB/CS cell array design method provides a relationship between bit line capacitance CB and memory cell capacitance CS, which must be satisfied for read operations. Also reported is a reference voltage generator circuit that uses a dummy memory cell. This circuit can generate an accurate reference voltage despite the variety of capacitors with differing characteristics that are contained in the NVFRAM. A 1-Mb NVFRAM prototype featuring the above technologies has been fabricated, using a 1.0-μm CMOS process. This chip has an access time of 60 ns and a die size of 15.7 × 5.79 mm2.
|Number of pages||9|
|Journal||IEEE Journal of Solid-State Circuits|
|Publication status||Published - 1996 Nov 1|
ASJC Scopus subject areas
- Electrical and Electronic Engineering