A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme

Hiroki Koike; Tetsuya Otsuki; Tohru Kimura; Masao Fukuma; Yoshihiro Hayashi; Yukihiko Maejima; Kazushi Amanuma; Nobuhiro Tanabe; Takeo Matsuki; Shinobu Saito; Tsuneo Takeuchi; Souta Kobayashi; Takemitsu Kunio; Takashi Hase; Yoichi Miyasaka; Nobuaki Shohata; Masahide Takada

doi:10.1109/jssc.1996.542307

A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme

Hiroki Koike, Tetsuya Otsuki, Tohru Kimura, Masao Fukuma, Yoshihiro Hayashi, Yukihiko Maejima, Kazushi Amanuma, Nobuhiro Tanabe, Takeo Matsuki, Shinobu Saito, Tsuneo Takeuchi, Souta Kobayashi, Takemitsu Kunio, Takashi Hase, Yoichi Miyasaka, Nobuaki Shohata, Masahide Takada

Research output: Contribution to journal › Article › peer-review

29 Citations (Scopus)

Abstract

This paper proposes three circuit technologies For achieving mega-bit-class nonvolatile ferroelectric RAM's (NVFRAM's). The proposed nondriven cell plate line write/read scheme (NDP scheme) accomplishes fast write/read operation equivalent to that of DRAM's. Problems and countermeasures in introducing this scheme into NVFRAM's are also discussed. A proposed optimized C_B/C_S cell array design method provides a relationship between bit line capacitance C_B and memory cell capacitance C_S, which must be satisfied for read operations. Also reported is a reference voltage generator circuit that uses a dummy memory cell. This circuit can generate an accurate reference voltage despite the variety of capacitors with differing characteristics that are contained in the NVFRAM. A 1-Mb NVFRAM prototype featuring the above technologies has been fabricated, using a 1.0-μm CMOS process. This chip has an access time of 60 ns and a die size of 15.7 × 5.79 mm².

Original language	English
Pages (from-to)	1625-1633
Number of pages	9
Journal	IEEE Journal of Solid-State Circuits
Volume	31
Issue number	11
DOIs	https://doi.org/10.1109/jssc.1996.542307
Publication status	Published - 1996 Nov
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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Koike, H., Otsuki, T., Kimura, T., Fukuma, M., Hayashi, Y., Maejima, Y., Amanuma, K., Tanabe, N., Matsuki, T., Saito, S., Takeuchi, T., Kobayashi, S., Kunio, T., Hase, T., Miyasaka, Y., Shohata, N., & Takada, M. (1996). A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme. IEEE Journal of Solid-State Circuits, 31(11), 1625-1633. https://doi.org/10.1109/jssc.1996.542307

Koike, H, Otsuki, T, Kimura, T, Fukuma, M, Hayashi, Y, Maejima, Y, Amanuma, K, Tanabe, N, Matsuki, T, Saito, S, Takeuchi, T, Kobayashi, S, Kunio, T, Hase, T, Miyasaka, Y, Shohata, N & Takada, M 1996, 'A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme', IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp. 1625-1633. https://doi.org/10.1109/jssc.1996.542307

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abstract = "This paper proposes three circuit technologies For achieving mega-bit-class nonvolatile ferroelectric RAM's (NVFRAM's). The proposed nondriven cell plate line write/read scheme (NDP scheme) accomplishes fast write/read operation equivalent to that of DRAM's. Problems and countermeasures in introducing this scheme into NVFRAM's are also discussed. A proposed optimized CB/CS cell array design method provides a relationship between bit line capacitance CB and memory cell capacitance CS, which must be satisfied for read operations. Also reported is a reference voltage generator circuit that uses a dummy memory cell. This circuit can generate an accurate reference voltage despite the variety of capacitors with differing characteristics that are contained in the NVFRAM. A 1-Mb NVFRAM prototype featuring the above technologies has been fabricated, using a 1.0-μm CMOS process. This chip has an access time of 60 ns and a die size of 15.7 × 5.79 mm2.",

author = "Hiroki Koike and Tetsuya Otsuki and Tohru Kimura and Masao Fukuma and Yoshihiro Hayashi and Yukihiko Maejima and Kazushi Amanuma and Nobuhiro Tanabe and Takeo Matsuki and Shinobu Saito and Tsuneo Takeuchi and Souta Kobayashi and Takemitsu Kunio and Takashi Hase and Yoichi Miyasaka and Nobuaki Shohata and Masahide Takada",

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AU - Saito, Shinobu

AU - Takeuchi, Tsuneo

AU - Kobayashi, Souta

AU - Kunio, Takemitsu

AU - Hase, Takashi

AU - Miyasaka, Yoichi

AU - Shohata, Nobuaki

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N2 - This paper proposes three circuit technologies For achieving mega-bit-class nonvolatile ferroelectric RAM's (NVFRAM's). The proposed nondriven cell plate line write/read scheme (NDP scheme) accomplishes fast write/read operation equivalent to that of DRAM's. Problems and countermeasures in introducing this scheme into NVFRAM's are also discussed. A proposed optimized CB/CS cell array design method provides a relationship between bit line capacitance CB and memory cell capacitance CS, which must be satisfied for read operations. Also reported is a reference voltage generator circuit that uses a dummy memory cell. This circuit can generate an accurate reference voltage despite the variety of capacitors with differing characteristics that are contained in the NVFRAM. A 1-Mb NVFRAM prototype featuring the above technologies has been fabricated, using a 1.0-μm CMOS process. This chip has an access time of 60 ns and a die size of 15.7 × 5.79 mm2.

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A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme

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