A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme

Hiroki Koike, Tetsuya Otsuki, Tohru Kimura, Masao Fukuma, Yoshihiro Hayashi, Yukihiko Maejima, Kazushi Amanuma, Nobuhiro Tanabe, Takeo Matsuki, Shinobu Saito, Tsuneo Takeuchi, Souta Kobayashi, Takemitsu Kunio, Takashi Hase, Yoichi Miyasaka, Nobuaki Shohata, Masahide Takada

Research output: Contribution to journalArticlepeer-review

29 Citations (Scopus)


This paper proposes three circuit technologies For achieving mega-bit-class nonvolatile ferroelectric RAM's (NVFRAM's). The proposed nondriven cell plate line write/read scheme (NDP scheme) accomplishes fast write/read operation equivalent to that of DRAM's. Problems and countermeasures in introducing this scheme into NVFRAM's are also discussed. A proposed optimized CB/CS cell array design method provides a relationship between bit line capacitance CB and memory cell capacitance CS, which must be satisfied for read operations. Also reported is a reference voltage generator circuit that uses a dummy memory cell. This circuit can generate an accurate reference voltage despite the variety of capacitors with differing characteristics that are contained in the NVFRAM. A 1-Mb NVFRAM prototype featuring the above technologies has been fabricated, using a 1.0-μm CMOS process. This chip has an access time of 60 ns and a die size of 15.7 × 5.79 mm2.

Original languageEnglish
Pages (from-to)1625-1633
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Issue number11
Publication statusPublished - 1996 Nov
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


Dive into the research topics of 'A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme'. Together they form a unique fingerprint.

Cite this