A single 5-V power supply 16-Mb dynamic random access memory (DRAM) has been developed, using a high-speed latched sensing scheme and a built-in self-test (BIST) function with a microprogrammed ROM, in which automatic test pattern generation procedures were stored by microcoded programs. The chip was designed using a double-level A1 wiring 0.55-µm CMOS technology. As a result, a 16-Mb CMOS DRAM with 55-ns typical access time and 130-mm2 chip area was attained by implementing 4.05-µm2 storage ceils. The installed ROM was composed of 18 words ×10 b, where the marching test and checkerboard scan write/read test procedures were stored, resulting in successful self-test operation. As the BIST circuit occupied 1 mm2 and the area overhead was about 1%, it proves to be promising for large-scale DRAM’s.
ASJC Scopus subject areas
- Electrical and Electronic Engineering