A 512kB embedded phase change memory with 416kB/s write throughput at 100μA cell write current

Satoru Hanzawa; Naoki Kitai; Kenichi Osada; Akira Kotabe; Yuichi Matsui; Nozomu Matsuzaki; Norikatsu Takaura; Masahiro Moniwa; Takayuki Kawahara

doi:10.1109/ISSCC.2007.373500

A 512kB embedded phase change memory with 416kB/s write throughput at 100μA cell write current

Satoru Hanzawa, Naoki Kitai, Kenichi Osada, Akira Kotabe, Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Masahiro Moniwa, Takayuki Kawahara

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

45 Citations (Scopus)

Abstract

An experimental 512kB embedded PCM uses a current-saving architecture in a 0.13μm 1.5V CMOS. The write scheme features a low-write-current resistive device and achieves 416kB/s write-throughput at 100μA cell current. A charge-transfer direct-sense scheme has a 16b parallel read access time of 9.9ns in an array drawing 280μA. A standby voltage scheme suppresses leakage current in the cell current path and increases the measured PCM cell resistance from 3 to 33MΩ.

Original language	English
Title of host publication	2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
Pages	474-475+616+471
DOIs	https://doi.org/10.1109/ISSCC.2007.373500
Publication status	Published - 2007 Sep 27
Event	54th IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco, CA, United States Duration: 2007 Feb 11 → 2007 Feb 15

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)	0193-6530

Other

Other	54th IEEE International Solid-State Circuits Conference, ISSCC 2007
Country	United States
City	San Francisco, CA
Period	07/2/11 → 07/2/15

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/ISSCC.2007.373500

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Hanzawa, S., Kitai, N., Osada, K., Kotabe, A., Matsui, Y., Matsuzaki, N., Takaura, N., Moniwa, M., & Kawahara, T. (2007). A 512kB embedded phase change memory with 416kB/s write throughput at 100μA cell write current. In 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers (pp. 474-475+616+471). [4242471] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2007.373500

A 512kB embedded phase change memory with 416kB/s write throughput at 100μA cell write current. / Hanzawa, Satoru; Kitai, Naoki; Osada, Kenichi; Kotabe, Akira; Matsui, Yuichi; Matsuzaki, Nozomu; Takaura, Norikatsu; Moniwa, Masahiro; Kawahara, Takayuki.

2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. 2007. p. 474-475+616+471 4242471 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hanzawa, S, Kitai, N, Osada, K, Kotabe, A, Matsui, Y, Matsuzaki, N, Takaura, N, Moniwa, M & Kawahara, T 2007, A 512kB embedded phase change memory with 416kB/s write throughput at 100μA cell write current. in 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers., 4242471, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, pp. 474-475+616+471, 54th IEEE International Solid-State Circuits Conference, ISSCC 2007, San Francisco, CA, United States, 07/2/11. https://doi.org/10.1109/ISSCC.2007.373500

Hanzawa S, Kitai N, Osada K, Kotabe A, Matsui Y, Matsuzaki N et al. A 512kB embedded phase change memory with 416kB/s write throughput at 100μA cell write current. In 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. 2007. p. 474-475+616+471. 4242471. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2007.373500

Hanzawa, Satoru ; Kitai, Naoki ; Osada, Kenichi ; Kotabe, Akira ; Matsui, Yuichi ; Matsuzaki, Nozomu ; Takaura, Norikatsu ; Moniwa, Masahiro ; Kawahara, Takayuki. / A 512kB embedded phase change memory with 416kB/s write throughput at 100μA cell write current. 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. 2007. pp. 474-475+616+471 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

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