TY - GEN
T1 - A 512kB embedded phase change memory with 416kB/s write throughput at 100μA cell write current
AU - Hanzawa, Satoru
AU - Kitai, Naoki
AU - Osada, Kenichi
AU - Kotabe, Akira
AU - Matsui, Yuichi
AU - Matsuzaki, Nozomu
AU - Takaura, Norikatsu
AU - Moniwa, Masahiro
AU - Kawahara, Takayuki
PY - 2007
Y1 - 2007
N2 - An experimental 512kB embedded PCM uses a current-saving architecture in a 0.13μm 1.5V CMOS. The write scheme features a low-write-current resistive device and achieves 416kB/s write-throughput at 100μA cell current. A charge-transfer direct-sense scheme has a 16b parallel read access time of 9.9ns in an array drawing 280μA. A standby voltage scheme suppresses leakage current in the cell current path and increases the measured PCM cell resistance from 3 to 33MΩ.
AB - An experimental 512kB embedded PCM uses a current-saving architecture in a 0.13μm 1.5V CMOS. The write scheme features a low-write-current resistive device and achieves 416kB/s write-throughput at 100μA cell current. A charge-transfer direct-sense scheme has a 16b parallel read access time of 9.9ns in an array drawing 280μA. A standby voltage scheme suppresses leakage current in the cell current path and increases the measured PCM cell resistance from 3 to 33MΩ.
UR - http://www.scopus.com/inward/record.url?scp=34548861504&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=34548861504&partnerID=8YFLogxK
U2 - 10.1109/ISSCC.2007.373500
DO - 10.1109/ISSCC.2007.373500
M3 - Conference contribution
AN - SCOPUS:34548861504
SN - 1424408539
SN - 9781424408535
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 474
EP - 476
BT - 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 54th IEEE International Solid-State Circuits Conference, ISSCC 2007
Y2 - 11 February 2007 through 15 February 2007
ER -