A 512 Kbit low-voltage NV-SRAM with the size of a conventional SRAM

T. Miwa; J. Yamada; H. Koike; T. Nakura; S. Kobayashi; N. Kasai; H. Toyoshima

A 512 Kbit low-voltage NV-SRAM with the size of a conventional SRAM

T. Miwa, J. Yamada, H. Koike, T. Nakura, S. Kobayashi, N. Kasai, H. Toyoshima

Research output: Contribution to conference › Paper › peer-review

Abstract

This paper describes two new circuit techniques for non-volatile SRAMs with back-up ferroelectric capacitors (NV-SRAMs). These circuits are able to overcome the size and low-voltage-reliability problems faced by the original NV-SRAM. A new 0.25-μm-design-rule four-metal-layer NV-SRAM cell occupies 9.7 μm², that is the same area as a 0.25-μm three-metal-layer SRAM cell. A high-voltage/negative-voltage plate line driver allows a low-voltage-operation NV-SRAM array's improving its nonvolatile retention characteristics. A 512-Kbit-test macro has also been designed with only one percent area overhead from a conventional SRAM macro.

Original language	English
Pages	129-132
Number of pages	4
Publication status	Published - 2001 Jan 1
Externally published	Yes
Event	2001 VLSI Circuits Symposium - Kyoto, Japan Duration: 2001 Jun 14 → 2001 Jun 16

Other

Other	2001 VLSI Circuits Symposium
Country/Territory	Japan
City	Kyoto
Period	01/6/14 → 01/6/16

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

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abstract = "This paper describes two new circuit techniques for non-volatile SRAMs with back-up ferroelectric capacitors (NV-SRAMs). These circuits are able to overcome the size and low-voltage-reliability problems faced by the original NV-SRAM. A new 0.25-μm-design-rule four-metal-layer NV-SRAM cell occupies 9.7 μm2, that is the same area as a 0.25-μm three-metal-layer SRAM cell. A high-voltage/negative-voltage plate line driver allows a low-voltage-operation NV-SRAM array's improving its nonvolatile retention characteristics. A 512-Kbit-test macro has also been designed with only one percent area overhead from a conventional SRAM macro.",

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AU - Miwa, T.

AU - Yamada, J.

AU - Koike, H.

AU - Nakura, T.

AU - Kobayashi, S.

AU - Kasai, N.

AU - Toyoshima, H.

PY - 2001/1/1

Y1 - 2001/1/1

N2 - This paper describes two new circuit techniques for non-volatile SRAMs with back-up ferroelectric capacitors (NV-SRAMs). These circuits are able to overcome the size and low-voltage-reliability problems faced by the original NV-SRAM. A new 0.25-μm-design-rule four-metal-layer NV-SRAM cell occupies 9.7 μm2, that is the same area as a 0.25-μm three-metal-layer SRAM cell. A high-voltage/negative-voltage plate line driver allows a low-voltage-operation NV-SRAM array's improving its nonvolatile retention characteristics. A 512-Kbit-test macro has also been designed with only one percent area overhead from a conventional SRAM macro.

AB - This paper describes two new circuit techniques for non-volatile SRAMs with back-up ferroelectric capacitors (NV-SRAMs). These circuits are able to overcome the size and low-voltage-reliability problems faced by the original NV-SRAM. A new 0.25-μm-design-rule four-metal-layer NV-SRAM cell occupies 9.7 μm2, that is the same area as a 0.25-μm three-metal-layer SRAM cell. A high-voltage/negative-voltage plate line driver allows a low-voltage-operation NV-SRAM array's improving its nonvolatile retention characteristics. A 512-Kbit-test macro has also been designed with only one percent area overhead from a conventional SRAM macro.

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A 512 Kbit low-voltage NV-SRAM with the size of a conventional SRAM

Abstract

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ASJC Scopus subject areas

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