Abstract
This paper describes two new circuit techniques for non-volatile SRAMs with back-up ferroelectric capacitors (NV-SRAMs). These circuits are able to overcome the size and low-voltage-reliability problems faced by the original NV-SRAM. A new 0.25-μm-design-rule four-metal-layer NV-SRAM cell occupies 9.7 μm2, that is the same area as a 0.25-μm three-metal-layer SRAM cell. A high-voltage/negative-voltage plate line driver allows a low-voltage-operation NV-SRAM array's improving its nonvolatile retention characteristics. A 512-Kbit-test macro has also been designed with only one percent area overhead from a conventional SRAM macro.
Original language | English |
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Pages | 129-132 |
Number of pages | 4 |
Publication status | Published - 2001 Jan 1 |
Externally published | Yes |
Event | 2001 VLSI Circuits Symposium - Kyoto, Japan Duration: 2001 Jun 14 → 2001 Jun 16 |
Other
Other | 2001 VLSI Circuits Symposium |
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Country | Japan |
City | Kyoto |
Period | 01/6/14 → 01/6/16 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering