A 500-MHz MRAM macro for high-performance SoCs

Noboru Sakimura, Ryusuke Nebashi, Hiroaki Honjo, Shinsaku Saito, Yuko Kato, Tadahiko Sugibayashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

A 500-MHz MRAM macro is developed using a 0.15-μm CMOS process and a newly developed MRAM process. The macro is designed using a 20.17-μm 2 5-transistor 2-magnetic tunnel junction (5T2MTJ) cell that has individual ports for writing and reading. An access time of less than 2 ns was obtained by employing a hierarchically-divided read bit line (RBL) and a high pre-charge sensing scheme. The operation speed is the highest among MRAMs that have been reported. This MRAM macro can coexist with the more area-effective 2TlMTJ-cell-based MRAM macro in SoCs.

Original languageEnglish
Title of host publicationProceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Pages261-264
Number of pages4
DOIs
Publication statusPublished - 2008 Dec 1
Externally publishedYes
Event2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 - Fukuoka, Japan
Duration: 2008 Nov 32008 Nov 5

Publication series

NameProceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

Other

Other2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
CountryJapan
CityFukuoka
Period08/11/308/11/5

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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