A 5-V Only 16-kbit Stacked-Capacitor MOS RAM

Mitsumasa Koyanagi, Yoshio Sakai, Norikazu Hashimoto, Masamichi Ishihara, Masanori Tazunoki

Research output: Contribution to journalArticle

10 Citations (Scopus)

Abstract

A novel one-transistor-type MOS RAM is discussed. This memory cell gives a remarkable area reduction and/or increase in storage capacitance by stacking the main portion of the storage capacitor on the address transistor, bit lines, or field oxides. It is called a stacked-capacitor (STC) RAM. This STC memory has a three-level poly-Si structure. The stacked capacitor has poly-Si-Si3N4-poly-Si (or Al) structure. A 16-kbit STC RAM has been fabricated with 3-µm technology and operated successfully. Memory performance is strikingly improved by using STC cells.

Original languageEnglish
Pages (from-to)1596-1601
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume27
Issue number8
DOIs
Publication statusPublished - 1980 Aug

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Koyanagi, M., Sakai, Y., Hashimoto, N., Ishihara, M., & Tazunoki, M. (1980). A 5-V Only 16-kbit Stacked-Capacitor MOS RAM. IEEE Transactions on Electron Devices, 27(8), 1596-1601. https://doi.org/10.1109/T-ED.1980.20076