A 5-V Only 16-kbit Stacked-Capacitor MOS RAM

Mitsumasa Koyanagi, Yoshio Sakai, Norikazu Hashimoto, Masamichi Ishihara, Masanori Tazunoki

Research output: Contribution to journalArticlepeer-review

10 Citations (Scopus)


A novel one-transistor-type MOS RAM is discussed. This memory cell gives a remarkable area reduction and/or increase in storage capacitance by stacking the main portion of the storage capacitor on the address transistor, bit lines, or field oxides. It is called a stacked-capacitor (STC) RAM. This STC memory has a three-level poly-Si structure. The stacked capacitor has poly-Si-Si3N4-poly-Si (or Al) structure. A 16-kbit STC RAM has been fabricated with 3-µm technology and operated successfully. Memory performance is strikingly improved by using STC cells.

Original languageEnglish
Pages (from-to)1596-1601
Number of pages6
JournalIEEE Transactions on Electron Devices
Issue number8
Publication statusPublished - 1980 Aug
Externally publishedYes

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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